When you link the HDL simulator with a Simulink® application, the simulator functions as the server. As the following diagram shows, the HDL Cosimulation blocks inside the Simulink model accept signals from the HDL module under simulation in the HDL simulator via the output ports on the Ports panes and return data via the input ports on the Ports panes.
Although you can bind the output ports of an HDL Cosimulation block to any signal in an HDL model hierarchy, you must use some caution when connecting signals to input ports. You want to verify that the signal you are binding to does not have other drivers. If it does, use resolved logic types; otherwise you may get unpredictable results.
If you need to use a signal that has multiple drivers and it
is resolved (for example, it is of VHDL type
, Simulink applies the resolution function at each time step
defined by the signal's Simulink sample rate. Depending on the
other drivers, the Simulink value may or may not get applied.
Furthermore, Simulink has no control over signal changes that
occur between its sample times.
Note: Verify that signals used in cosimulation have read/write access. You can check read/write access through the HDL simulator—see HDL simulator documentation for details.
This rule applies to all signals on the Ports, Clocks, and Simulation panes and to signals added to the model in any other manner.
HDL Verifier™ software supports the use of multirate signals, signals that are sampled or updated at different rates, in a single HDL Cosimulation block. An HDL Cosimulation block exchanges data for each signal at the Simulink sample rate for that signal. For input signals, an HDL Cosimulation block accepts and honors all signal rates.
The HDL Cosimulation block also lets you specify an independent sample time for each output port. You must explicitly set the sample time for each output port, or accept the default. Using this setting lets you control the rate at which Simulink updates an output port by reading the corresponding signal from the HDL simulator.
Use the Simulink Zero-Order Hold block to apply a zero-order hold (ZOH) on continuous signals that are driven into an HDL Cosimulation block.
The HDL Verifier HDL Cosimulation Block links hardware components that are concurrently simulating in the HDL simulator to the rest of a Simulink model.
You can link Simulink and the HDL simulator in two possible ways:
As a single HDL Cosimulation block fitted into the framework of a larger system-oriented Simulink model.
As a Simulink model made up of a collection of HDL Cosimulation blocks, each representing a specific hardware component.
The block mask contains panels for entering port and signal information, setting communication modes, adding clocks (Incisive® and ModelSim® only), specifying pre- and post-simulation Tcl commands (Incisive and ModelSim only), and defining the timing relationship.
After you code one of your model's components in VHDL or Verilog and simulate it in the HDL simulator environment, you integrate the HDL representation into your Simulink model as an HDL Cosimulation block. There is one block for each supported HDL simulator. These blocks are located in the Simulink Library, within the HDL Verifier block library. As an example, the block for use with Mentor Graphics® ModelSim is shown in the next figure.
You configure an HDL Cosimulation block by specifying values for parameters in a block parameters dialog box. The HDL Cosimulation block parameters dialog box consists of tabbed panes that specify the following information:
Ports Pane: Block input and output ports that correspond to signals, including internal signals, of your HDL design, and an output sample time.
Connection Pane: Type of communication and related settings to be used for exchanging data between simulators.
Timescales Pane: The timing relationship between Simulink software and the HDL simulator.
Clocks Pane (Incisive and ModelSim only): Optional rising-edge and falling-edge clocks to apply to your model.
Simulation Pane (Incisive and ModelSim only): Tcl commands to run before and after a simulation.