If your HDL application needs to send HDL data to a MATLAB^{®} function,
you may first need to convert the data to a type supported by MATLAB and
the HDL
Verifier™ software.

To program a MATLAB function for an HDL model, you must understand the type conversions required by your application. You may also need to handle differences between the array indexing conventions used by the HDL you are using and MATLAB (see following section).

The data types of arguments passed in to the function determine the following:

The types of conversions required before data is manipulated

The types of conversions required to return data to the HDL simulator

The following table summarizes how the HDL
Verifier software
converts supported VHDL^{®} data types to MATLAB types based
on whether the type is scalar or array.

**VHDL-to-MATLAB Data Type Conversions**

VHDL Types... | As Scalar Converts to... | As Array Converts to... |
---|---|---|

`STD_LOGIC` , `STD_ULOGIC` ,
and `BIT` | A character that matches the character literal for the desired logic state. | |

`STD_LOGIC_VECTOR` , `STD_ULOGIC_VECTOR` , `BIT_VECTOR` , `SIGNED` ,
and `UNSIGNED` | A column vector of characters (as defined in VHDL Conversions for the HDL Simulator) with one bit per character. | |

Arrays of `STD_LOGIC_VECTOR` , `STD_ULOGIC_VECTOR` , `BIT_VECTOR` , `SIGNED` ,
and `UNSIGNED` | An array of characters (as defined above) with a size that is equivalent to the VHDL port size. | |

`INTEGER` and `NATURAL` | Type `int32` . | Arrays of type `int32` with a size that is
equivalent to the VHDL port size. |

`REAL` | Type `double` . | Arrays of type `double` with a size that is
equivalent to the VHDL port size. |

`TIME` | Type `double` for time values in seconds and
type `int64` for values representing simulator time
increments (see the description of the `'time'` option
in `hdldaemon` ). | Arrays of type `double` or `int64` with
a size that is equivalent to the VHDL port size. |

Enumerated types | Character vector that contains the MATLAB representation
of a VHDL label or character literal. For example, the label `high` converts
to `'high'` and the character literal `'c'` converts
to `'''c'''` . | Cell array of character vectors with each element equal to
a label for the defined enumerated type. Each element is the MATLAB representation
of a VHDL label or character literal. For example, the vector ```
(one,
'2', three)
``` converts to the column vector ```
['one';
'''2'''; 'three']
``` . A user-defined enumerated type that contains
only character literals, and then converts to a vector or array of
characters as indicated for the types `STD_LOGIC_VECTOR` , `STD_ULOGIC_VECTOR` , `BIT_VECTOR` , `SIGNED` ,
and `UNSIGNED` . |

The following table summarizes how the HDL
Verifier software
converts supported Verilog^{®} data types to MATLAB types. The
software supports only scalar data types for Verilog.

**Verilog-to-MATLAB Data Type Conversions**

Verilog Types... | Converts to... |
---|---|

`wire` , `reg` | A character or a column vector of characters that matches the character literal for the desired logic states (bits). |

The following table summarizes how the HDL Verifier software converts supported SystemVerilog data types to MATLAB types. The software supports only scalar data types for SystemVerilog.

**SystemVerilog-to-MATLAB Data Type Conversions**

SystemVerilog Types... | Converts to... |
---|---|

`wire` , `reg` ,
`logic` | A character or a column vector of characters that matches the character literal for the desired logic states (bits). |

`integer`
| A 32-element column vector of characters that matches the character literal for the desired logic states (bits). |

Multidimensional arrays of
`reg`

/`wire`

/`logic`

are
not supported.

In HDL, you have the flexibility to define a bit-vector with either MSB-0 or LSB-0 numbering. In MATLAB, bit-vectors are always considered LSB-0 numbering. In order to prevent data corruption, it is recommended that you use LSB-0 indexing for your HDL interfaces.

If you define a logic vector in HDL as:

signal s1 : std_logic_vector(7 downto 0);

It is mapped to int8 in MATLAB, with s1[7] as the MSB. Alternatively, if you define your logic vector as:

signal s1 : std_logic_vector(0 to 7);

It is mapped to int8 in MATLAB, with s1[0] as the MSB.

In multidimensional arrays, the same underlying OS memory buffer
maps to different elements in MATLAB and the HDL simulator (this
mapping only reflects different ways the different languages offer
for naming the elements of the same array). When you use both the `matlabtb`

and `matlabcp`

functions,
be careful to assign and interpret values consistently in both applications.

In HDL, a multidimensional array declared as:

type matrix_2x3x4 is array (0 to 1, 4 downto 2) of std_logic_vector(8 downto 5);

has a memory layout as follows:

bit 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24- dim1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 dim2 4 4 4 4 3 3 3 3 2 2 2 2 4 4 4 4 3 3 3 3 2 2 2 2 dim3 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5

This same layout corresponds to the following MATLAB 4x3x2 matrix:

bit 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24- dim1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 dim2 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2 2 2 2 3 3 3 3 dim3 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2

Therefore, if H is the HDL array and M is the MATLAB matrix, the following indexed values are the same:

b1 H(0,4,8) = M(1,1,1) b2 H(0,4,7) = M(2,1,1) b3 H(0,4,6) = M(3,1,1) b4 H(0,4,5) = M(4,1,1) b5 H(0,3,8) = M(1,2,1) b6 H(0,3,7) = M(2,2,1) ... b19 H(1,3,6) = M(3,2,2) b20 H(1,3,5) = M(4,2,2) b21 H(1,2,8) = M(1,3,2) b22 H(1,2,7) = M(2,3,2) b23 H(1,2,6) = M(3,3,2) b24 H(1,2,5) = M(4,3,2)

You can extend this indexing to N-dimensions. In general, the dimensions—if numbered from left to right—are reversed. The right-most dimension in HDL corresponds to the left-most dimension in MATLAB.

Depending on how your simulation MATLAB function uses the data it receives from the HDL simulator, you may need to code the function to convert data to a different type before manipulating it. The following table lists circumstances under which you would require such conversions.

**Required Data Conversions**

If You Need the Function to... | Then... |
---|---|

Compute numeric data that is received as a type other than `double` |
Use the datas(inc+1) = double(idata); |

Convert a standard logic or bit vector to an unsigned integer or positive decimal |
Use the uval = mvl2dec(oport.val) This example assumes the standard logic or bit vector is
composed of the character literals The See |

Convert a standard logic or bit vector to a negative decimal |
Use the following application of the
suval = mvl2dec(oport.val, true); This example assumes the standard logic or bit vector is
composed of the character literals |

The following code excerpt illustrates data type conversion of data passed in to a callback:

InDelayLine(1) = InputScale * mvl2dec(iport.osc_in',true);

This example tests port values of VHDL type `STD_LOGIC`

and `STD_LOGIC_VECTOR`

by
using the `all`

function as follows:

all(oport.val == '1' | oport.val == '0')

This example returns `True`

if all elements
are `'1'`

or `'0'`

.

If your simulation MATLAB function needs to return data to the HDL simulator, you may first need to convert the data to a type supported by the HDL Verifier software. The following tables list circumstances under which such conversions are required for VHDL and Verilog.

When data values are returned to the HDL simulator, the char array size must match the HDL type, including leading zeroes, if applicable. For example:

oport.signal = dec2mvl(2)

will only work if `signal`

is a 2-bit type
in HDL. If the HDL type is anything else, you *must* specify
the second argument:

oport.signal = dec2mvl(2, N)

where N is the number of bits in the HDL data type.

**VHDL Conversions for the HDL Simulator**

To Return Data to an IN Port of Type... | Then... |
---|---|

`STD_LOGIC` , `STD_ULOGIC` ,
or `BIT` |
Declare the data as a character that matches the character
literal for the desired logic state. For
iport.s1 = 'X'; %STD_LOGIC iport.bit = '1'; %BIT |

`STD_LOGIC_VECTOR` , `STD_ULOGIC_VECTOR` , `BIT_VECTOR` , `SIGNED` ,
or `UNSIGNED` |
Declare the data as a column vector or row vector of characters (as defined above) with one bit per character. For example: iport.s1v = 'X10ZZ'; %STD_LOGIC_VECTOR iport.bitv = '10100'; %BIT_VECTOR iport.uns = dec2mvl(10,8); %UNSIGNED, 8 bits |

Array of `STD_LOGIC_VECTOR` , `STD_ULOGIC_VECTOR` , `BIT_VECTOR` , `SIGNED` ,
or `UNSIGNED` | Declare the data as an array of type character with a size that is equivalent to the VHDL port size. See Array Indexing Differences Between MATLAB and HDL. |

`INTEGER` or` NATURAL` | Declare the data as an array of type iport.int = int32(1:10)'; |

`REAL` |
Declare the data as an array of type iport.dbl = ones(2,2); |

`TIME` | Declare a VHDL
iport.t1 = int64(1:10)'; %Simulator time %increments iport.t2 = 1e-9; %1 nsec |

Enumerated types |
Declare the data as a character vector for scalar ports or a
cell array of character vectors for array ports with each
element equal to a label for the defined enumerated type. The
iport.char = {'''A''', '''B'''}; %Character %literal iport.udef = 'mylabel'; %User-defined label |

Character array for standard logic or bit representation |
Use the oport.slva =dec2mvl([23 99],8)'; |

**Verilog Conversions for the HDL Simulator**

To Return Data to an `input` Port
of Type... | Then... |
---|---|

`reg` , `wire` |
Declare the data as a character or a column vector of characters that matches the character literal for the desired logic state. For example: iport.bit = '1'; |

**SystemVerilog Conversions for the HDL Simulator**

To Return Data to an `input` Port
of Type... | Then... |
---|---|

`reg` , `wire` ,
`logic` |
Declare the data as a character or a column vector of characters that matches the character literal for the desired logic state. For example: iport.bit = '1'; |

`integer` | Declare the data as a 32-element column vector of characters (as defined above) with one bit per character. |

Multidimensional arrays of
`reg`

/`wire`

/`logic`

are
not supported.

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