The HDL Verifier™ direct feedthrough feature eliminates latency in HDL designs with pure combinational datapaths. Direct feedthrough means that the output is controlled directly by the value of an input port. With direct feedthrough enabled, the input value change propagates to the output ports in zero time, thus eliminating the one output-sample delay.
You will still experience block simulation latency for pure combinational circuits even with direct feedthrough applied if your HDL design contains any of the following conditions:
A different sample time between the input and output ports
A nonuniform sampling time among the output ports
The input/output signals are framed
When you are simulating a sequential circuit that has a register on the datapath from input port to output port, specifying direct feedthrough does not affect the timing of that datapath.
Read the following sections to learn more about using direct feedthrough:
You can also examine the example "Simulate HDL Design with Pure Combinational Datapath" to see how you might apply this feature.
To apply direct feedthrough:
Double-click on the HDL Cosimulation block.
Click on the Ports pane.
Select Enable direct feedthrough for HDL design with pure combinational datapath.
In the Simulink® model, the HDL cosimulation block has a path from input to output that contains only pure combinational logic.
Without direct feedthrough applied, the HDL output has a one-sample delay compared with the Simulink reference signal, as shown in the following Scope window.
This delay occurs from simulating a pure combinational HDL design without applying direct feedthrough.
With direct feedthrough applied, the change of input signal is propagated to the output port in zero time as expected, as shown in the following Scope window.