Documentation

Prepare IP-XACT File for Import

To customize the TLM interface of the component you want to generate, you can import your own IP-XACT XML file into the TLM generator.

For more information about importing the IP-XACT file, see Select TLM Mapping Options.

Required Information for Imported IP-XACT Files

All IP-XACT XML files must contain information specific to MathWorks®, defined in elements within the component. If this information is not present, the TLM generator cannot parse the IP-XACT file.

The following parameter name-value pairs are required for <spirit:component>:

  • <spirit:parameter>

         <spirit:name>MWVendor</spirit:name>

         <spirit:value>MathWorks</spirit:value>

    </spirit:parameter>

  • <spirit:parameter>

         <spirit:name>MWVersion</spirit:name>

         <spirit:value>1.0</spirit:value>

    </spirit:parameter>

  • <spirit:parameter>

         <spirit:name>MWModel</spirit:name>

         <spirit:value>name_of_model</spirit:value>

    </spirit:parameter>

  • <spirit:parameter>

         <spirit:name>MWBlock</spirit:name>

         <spirit:value>name_of_block</spirit:value>

    </spirit:parameter>

This image shows these required elements within an IP-XACT XML file.

Bus Interface Definition with No Memory Map

General Guidelines

Write the bus definitions for your model according to the IEEE® Standard for IP-XACT 1685-2009.

If you want to use the Simulink® mapping, all bus interfaces that contain Simulink mapping must be slave interfaces.

Each bus interface with no memory map must have one of the following element arrangements for Simulink mapping:

  • No mapping to Simulink

  • Mapping to Simulink inputs, Simulink outputs, or a mix of inputs and outputs

  • Mapping to Simulink tunable parameters

Although each bus interface can have only one arrangement, the IP-XACT file can contain multiple bus interface definitions, each having a different arrangement.

Simulink Mapping with No Memory Map

Each <spirit:busInterface> definition containing a Simulink mapping is mapped to the TLM target socket. Within the <spirit:parameters> tag, add <spirit:parameter> name-value pairs that define the Simulink mapping. For example:

<spirit:parameter>
    <spirit:name>MWMapInput</spirit:name>
    <spirit:value>input_1</spirit:value>
</spirit:parameter>

This image shows some bus interfaces that are mapped to Simulink inputs.

The inputs are mapped together in one bus interface definition. The outputs are in a separate bus interface. The filter coefficients are in another, separate bus interface.

Alternatively, you can define the inputs and outputs together in a single bus interface definition. However, the filter coefficients must remain in their own separate bus interface definition.

Bus Interface Definition with Memory Mapping

General Guidelines

Write the bus definitions for your model according to the IEEE Standard for IP-XACT 1685-2009. The following permissions apply:

  • Input registers — Write-only or read-write

  • Output registers — Read-only or read-write

  • Parameters register — Read-only, write-only, or read-write, depending on your requirements

Make the spirit size of each register, in bits, greater than or equal to the size of that Simulink input, output, or parameter.

If you want to use the Simulink mapping, all bus interfaces that contain the Simulink mapping must be slave interfaces.

Simulink Mapping Within a Memory Map

If you have a memory map reference in the bus interface, then you must express the Simulink mapping in the memory map, not in the bus interface.

The Simulink mapping for each register can consist of the following element arrangements:

  • No mapping to Simulink (that is, no mapping information is needed in the register)

  • Mapping to Simulink inputs, Simulink outputs, or a mix of inputs and outputs

  • Mapping to Simulink tunable parameters

Registers cannot have multiple input-outputs. However, the bus interface can contain multiple registers, each having a different arrangement.

To add inputs, outputs, or parameters to the IP-XACT file:

  1. Each <spirit:busInterface> definition containing a Simulink mapping is mapped to the TLM target socket. Add a <spirit:parameter> name-value pair that indicates to the TLM generator that there is Simulink mapping in the memory map:

    <spirit:parameter>
        <spirit:name>MWMap</spirit:name>
        <spirit:value>true</spirit:value>
    </spirit:parameter>
  2. In each <spirit:memoryMap> interface, in each <spirit:register> definition, within the <spirit:parameters> tag, add a <spirit:parameter> name-value pair with the Simulink mapping.

    <spirit:parameter>
        <spirit:name>MWMapInput</spirit:name>
        <spirit:value>input1</spirit:value>
    </spirit:parameter>
  3. To optionally specify field locations within a register, specify a <spirit:field> definition in the <spirit:register>. Use the <spirit:bitWidth> and <spirit:bitOffset> tags to define each <spirit:field>. Include the <spirit:parameter> name-value pair with the Simulink mapping in the <spirit:field> definition.

    <spirit:field>
       <spirit:name>OUTPUT_1</spirit:name>
       <spirit:bitOffset>32</spirit:bitOffset>
       <spirit:bitWidth>32</spirit:bitWidth>
       <spirit:access>read-only</spirit:access>
       <spirit:parameters>
          <spirit:parameter>
             <spirit:name>MWMapOutput</spirit:name>
             <spirit:value>output_1</spirit:value>
          </spirit:parameter>
       </spirit:parameters>
    </spirit:field>
    

This image demonstrates this arrangement for a Simulink input.

Mapping to a Signal Port

You can generate an unregistered sc_signal port. When the step function is executed, it reads the current value of the sc_in ports, passes them all to the step function, executes the step function and writes the step function result in the sc_out ports.

To add input and output ports, specify the following in your IP-XACT file:

  1. Specify the port as <spirit:port> of type <spirit:wire>.

  2. Specify the port direction as <spirit:direction>. Set the direction to in, to generate an sc_in port. Set direction to out to generate an sc_out port.

  3. By default, the data type of the port is the same as the subsystem input or output. You can optionally define a data type for the port by describing it in <spirit:wireTypeDef>.

This image shows an example of mapping to ports.

Related Topics

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