When you create a Simulink® model that includes one or more HDL Verifier™ Cosimulation blocks, you might want to adjust certain Simulink parameter settings to best meet the needs of HDL modeling. For example, you might want to adjust the value of the Stop time parameter in the Solver pane of the Model Configuration Parameters dialog box.
You can adjust the parameters individually or you can use DSP System Toolbox™ Simulink model templates to automatically configure the Simulink environment with the recommended settings for digital signal processing modeling.
The default settings for
For more information on DSP System Toolbox Simulink model templates, see the DSP System Toolbox documentation.
To determine an available socket number use:
ttcp -a a
You can check the connection status by clicking the Update diagram button or by selecting Simulation > Update Diagram. If your have an error in the connection, Simulink will notify you.
The MATLAB® command
also be used to check the connection status. If a -1 is returned,
then there is no connection with the HDL simulator.
In general, the last stage of cosimulation is to run and test your model. There are some steps you must be aware of when changing your model during or between cosimulation sessions. although your testing methods may vary depending on which HDL simulator you have, You can review these steps in Run and Test Test Bench Cosimulation Model.
You can run the cosimulation in one of three ways:
Start the HDL simulator and load your HDL design. For test bench cosimulation, begin simulation first in the HDL simulator. Then, in Simulink, click Simulation > Run or the Run Simulation button. Simulink runs the model and displays any errors that it detects. You can alternate between the HDL simulator and Simulink GUIs to monitor the cosimulation results.
For component cosimulation, start the simulation in Simulink first, then begin simulation in the HDL simulator.
You can specify "GUI" as the property value for the run mode parameter of the HDL Verifier HDL simulator launch command, but since using the GUI is the default mode for HDL Verifier, you do not have to.
Running your cosimulation session using the command-line interface allows you to interact with the HDL simulator during cosimulation, which can be helpful for debugging.
To use the CLI, specify "CLI" as the property value for the run mode parameter of the HDL Verifier HDL simulator launch command.
Caution Close the terminal window by entering "quit -f" at the command prompt. Do not close the terminal window by clicking the "X" in the upper right-hand corner. This causes a memory-type error to be issued from the system. This is not a bug with HDL Verifier but just the way the HDL simulator behaves in this context.
You can type CTRL+C to interrupt and terminate the simulation in the HDL simulator but this action also causes the memory-type error to be displayed.
Running your cosimulation session in batch mode allows you to keep the process in the background, reducing demand on memory by disengaging the GUI.
To use the batch mode, specify "Batch" as the property value
for the run mode parameter of the HDL Verifier HDL simulator
launch command. After you issue the HDL Verifier HDL simulator
launch command with batch mode specified, start the simulation in Simulink.
To stop the HDL simulator before the simulation is completed, issue
If you wish to reset a clock during a cosimulation, you can do so in one of these ways:
By entering HDL simulator
at the HDL simulator command prompt
By specifying HDL simulator
in the Post- simulation command text field on
the Simulation pane of the HDL Verifier Cosimulation
block parameters dialog box.
See also Clock, Reset, and Enable Signals.
If you change any part of the Simulink model, including the HDL Cosimulation block parameters, update the diagram to reflect those changes. You can do this update in one of the following ways:
Rerun the simulation
Click the Update diagram button
Select Simulation > Update Diagram
In the HDL simulator, you cannot control the order in which clock signals (rising-edge or falling-edge) defined in the HDL Cosimulation block are applied, relative to the data inputs driven by these clocks. If you are careful to verify the relationship between the data and active edges of the clock, you can avoid race conditions that could create differing cosimulation results. See Race Conditions in HDL Simulators.