Sigma Delta ADC with Noise

This example shows a simple implementation of a sigma delta analog-to-digitial converter. Inputs in the range 0 to Vref (=1V) are integrated and then reset, the time of integration as a proportion of the total integrate-reset period providing the measurement. Demodulation of the pulses is performed by a low-pass filter. The Asynchronous Sample & Hold block behaves like an edge-triggered D-type flip-flop, passing input U to output Y only on a rising edge of the clock. This model can be used to explore and understand the effect of op-amp impairments such as equivalent input noise on converter accuracy. To turn off the noise, open block Vn and select 'Disabled' for the noise mode.

Was this topic helpful?