Asynchronous Sample & Hold

Output sample-and-hold signal with external trigger


Physical Signals/Discrete


The Asynchronous Sample & Hold block sets the output signal, Y, equal to the input signal, U, when the rising edge of the trigger input becomes greater than zero. Use this block, in conjunction with other physical signal blocks, to model discrete and event-based behaviors.

Both inputs and the output are physical signals.


Initial output

The value of the output signal at time zero. The output of the block remains at this value until the block is triggered by a rising trigger signal becoming positive. The default value is 0.


The block has two physical signal input ports and one physical signal output port.


The Asynchronous PWM Voltage Source example illustrates how you can use the Asynchronous Sample & Hold block to build components with more complex behaviors. For an alternative discrete-time implementation, see the Discrete-Time PWM Voltage Source example. The discrete-time version is better suited to fixed-step solvers and hardware-in-the-loop applications, whereas the asynchronous implementation is better suited to fast desktop simulation using variable-step solvers.

See Also

Introduced in R2011b

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