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Neutral Point Clamp Inverter and Dead Time

This example shows the impact of dead time and semiconductor failure inside a three-level PWM converter.

Description

This model represents two identical circuits modeling a 50kW, 380V, 50Hz, three-phase, three-level inverter. The IGBT inverter uses SPWM technique, (8kHz carrier frequency) to convert DC power from a +/-200Vdc source to 220V AC, 50Hz. The inverter feeds a 50kW resistive load through a 75kVA 220/380V transformer. L-C filters are used at the converter output to filter out harmonic frequencies Fh generated mainly around multiples of 8kHz switching frequency (Fh=n*8000 +/-k*50Hz). The 12 inverter pulses required by the inverter are generated by the PWM Generator block. The system operates in open loop at a constant modulation index.

Circuit 1 uses the Three-Level Bridge block to model the inverter. Circuit 2 uses individual IGBTs and diodes blocks. The dead time is simulated with the On/Off Delay block and it is applied on the circuit 1 only.

Simulation

Comparing simution results with the Three-Level Bridge block and the user-built converter - no dead time

1. Set the Manual Switch block to its upper position to disable dead time effect on circuit 1. 2. Start the simulation and observe the inverter and load voltages of circuit 1 and circuit 2 which are superimposed on Scope1. 3. Once the simulation is completed, open the Powergui and select FFT Analysis to display the frequency spectrum of signals saved in the ScopeData1 structure. 4. The FFT will be performed on the last cycle of the selected signal. You can analyze either inverter voltages (select input Vab_inv_1_2) or load voltages (select input Vab_load_1_2). Select Signal number 1 or Signal number 2 to analyze voltages of circuit 1 or circuit 2 and click on Display to observe the 0-25000 Hz frequency spectrum.

As expected, at the inverter output, harmonics are observed around multiples of the switching frequency (8 kHz). At the load terminals, these high frequency harmonics are considerably reduced by LC filters. Also, note that the LC filters creates a resonance which produces additional harmonics around 4.4 kHz. The fundamental component and Total Harmonic Distortion (THD) are displayed above the spectrum graph. For both circuits THD is 1.27% on the load side and fundamental voltage is 380 V rms (537.6 V peak).

Impact of dead time on fundamental voltage and harmonic distortion

In a three-level voltage-sourced converter (VSC) using ideal switches, the two pairs of pulses sent to each arm could be complementary. For example, for phase A, IGBT1 is complementary of IGBT3 and IGBT2 is complementary of IGBT4. However, in practical VSCs the turn-off of semiconductor switches is delayed because of the storage effect. Therefore, a time delay of a few microseconds (storage time + safety margin) is required to allow complete extinction of the IGBT which is switched off before switching on the other IGBT. Otherwise, a short-circuit could result on the DC bus.

5. Set the Manual Switch block to its lower position. 6. Run the simulation and compare the two load voltage waveforms on Scope1 and their fundamental values on the two Display blocks. 7. Do the FFT analysis with the Powergui block. You will note that the dead time decreases fundamental component and increases distortion.

Results from frequency analysis are summarized in the table shown in the model. This table indicates that the amplitude of the main characteristic frequencies (around 8 kHz) increases slightly (from 0.74% to 0.82 %) when the dead time is used. The THD increase is caused mainly by the introduction of non characteristic low frequency harmonics (mainly 5th and 7th ).

Simulating a diode failure fault inside the three-level converter

8. Set the manual switch to its upper position to disable the dead time and for the two inverters to generate identical waveforms. 9. Open the Three-Level Converter (Detailed) subsystem. Note that an ideal switch block labeled D5 Open is connected in series with the neutral clamping diode D5 of phase A. 10. Open the Stair Generator block menu and in the Time parameter, change the 100 multiplier to 1. The block will now order a switch opening at t=0.25 s, thus simulating a diode failure in open circuit. 11. Start simulation and compare circuit 1 and circuit 2 waveforms on Scope1.

Diode D5 current and VaN voltage of inverter 2 are displayed on Scope2. When D5 fails open, its clamping effect to neutral is disabled and VaN voltage oscillates between +200V and -200 V (instead of +200V and zero). This unsymmetrical operation of phase A inverter arm introduces low frequency, odd and even harmonics.

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