Thyristor-Based HVDC Transmission System (Detailed Model)

This example shows the steady-state and transient performance of a 12-pulse, 1000 MW (500 kV-2kA) 50/60 Hz HVDC transmission system

Silvano Casoria (Hydro-Quebec)


A 1000 MW (500 kV, 2kA) DC interconnection is used to transmit power from a 500 kV, 5000 MVA, 60 Hz network to a 345 kV, 10 000 MVA, 50 Hz network.

The rectifier and the inverter are 12-pulse converters using two 6-pulse thyristor bridges connected in series. The rectifier and the inverter are interconnected through a 300 km distributed parameter line and two 0.5 H smoothing reactors. The transformer tap changers are not simulated and fixed taps are assumed. Open the two transformer blocks in the Rectifier and Inverter subsystems to see the factors applied on the primary voltage: 0.90 on rectifier side and 0.96 on inverter side. Reactive power required by the converters is provided by a set of capacitor banks plus 11th, 13th and high pass filters for a total of 600 Mvar on each side. Two circuit breakers are used to apply faults on the inverter AC side and rectifier DC side.

DC Protection functions are implemented in each converter. At the rectifier the DC fault protection will detect and force the delay angle into the inverter region so to extinguish the fault current. At the inverter the commutation failure prevention control will detect AC faults and reduce the maximum delay angle limit in order to decrease the risk of commutation failure. The Low AC voltage detection blocks will lock the DC fault protection when a drop in the AC voltage is detected. The Master Control block initiates the starting and stopping of the converters as well as the ramping up and down of the current references. The power system and the control system are both discretized for a sample time Ts=50 us. Notice that the "Model initialization" function of the model automatically sets Ts = 50e-6 in your MATLAB® workspace. A description of the control systems is provided in the HVDC Transmission System Case Study of the User's Manual.


The system is programmed to start and reach a steady state. Then steps are applied on the reference current of the rectifier and on the inverter reference voltage in order to observe the dynamic response of the regulators. Finally, a stop sequence is initiated to bring the DC power down before blocking the converters. Start the simulation. Open the RECTIFIER and INVERTER scopes (in the Data Acquisition subsystem) and observe the DC line voltage on trace 1 (1pu = 500 kV) and the DC line current (reference and measured values) on trace 2 (1pu = 2kA).

Start-up and Stop

In the Master Control, the converters are deblocked and started by ramping the rectifier and inverter reference current. At t = 0.02 s (i.e. when the converters at deblocked), the reference current is ramped to reach the minimum value of 0.1 pu in 0.3 s (0.33 pu/s). At the end of this first ramp (t = 0.32 s) the DC line is charged at its nominal voltage and DC voltage reaches steady-state. At t= 0.4 s, the reference current is ramped from 0.1 pu to 1 pu (2kA) in 0.18 s (5 pu/s). At the end of this starting sequence (t=0.58 s) , the DC current reaches steady state. The RECTIFIER then controls the current and the INVERTER controls the voltage. In steady-state, the alpha firing angles (trace 3) are 16.5 degrees and 143 degrees respectively on the RECTIFIER and INVERTER sides. The exctinction angle gamma (minimum value) is measured at the INVERTER and shown in trace 4. In steady-state, the minimum value is between 22 and 24 degrees. The control mode of operation (an integer between 0 to 6) is shown in trace 4 (0= blocked; 1=Current control; 2=Voltage control; 3=Alpha minimum limitation; 4=Alpha maximum limitation; 5=Forced or constant alpha; 6=Gamma control). At t = 1.4 s the Stop sequence is initiated by ramping down the current to 0.1 pu. At t = 1.6 s a Forced-alpha at the Rectifier extinguishes the current and at the Inverter the Forced-alpha brings down the DC voltage. At t = 1.7 s the pulses are blocked in both converters.

Step response of current and voltage regulators

Verify in the Master Control that the "Enable Ref. Current Step" switch is in the upper position. This switch is used to apply a step on the reference voltage. Also verify that the reference voltage step is enabled in the Inverter Control. At t=0.7 s, a -0.2 pu step is first applied on the reference current (decrease from 1 pu to 0.8 pu ) and at t=0.8 s, the reference current is reset to its 1 pu original value.The current stabilizes in approximately 0.1 seconds. Steps are also applied on the reference voltage of the inverter (-0.1 pu / +0.1 pu at t=1.0 s / 1.1s).

DC line fault at the rectifier

Deactivate the steps applied on the current reference and on the voltage reference in the Master Control and in the inverter control respectively by setting the switches in lower position. In the DC Fault block, change to 1 the 100 multiplication factor in the Switching times so that a fault is now applied at t = 0.7 s. Reduce the Simulation stop time from 2 to 1.4 s. The DC Fault protection (DCPROT) in the rectifier is activated by default. Open the FAULT scope to observe the DC fault current. Restart the simulation.

At fault application the DC current quickly increases to 2.3 pu and the DC voltage falls to zero at the rectifier. This DC voltages drop is seen by the Voltage Dependent Current Order Limiter (VDCOL) which reduces the reference current to 0.3 pu at the rectifier. A DC current still continues to circulate in the fault. Then, at t = 0.77 s, the rectifier alpha firing angle is forced to 166 degrees by the DC protection because a DC voltage drop is detected (VdL< 0.5 pu for more than 70 ms). The rectifier now operates in inverter mode. The DC line voltage becomes negative and the energy stored in the line is returned to the AC network, causing rapid extinction of the fault current at its next zero-crossing. Then, alpha is released at t = 0.87 s and the normal DC voltage and current recover in approximately 0.4 s.

AC line-to-ground fault at the inverter

In the DC Fault block, change the multiplication factor of 1 in the Switching times to 100, so that the DC fault is now eliminated. In the A-G Fault block, change to 1 the 100 multiplication factor in the Switching times so that a 6 cycles line-to-ground fault is now applied at t = 0.7 s. The Low AC voltage detection (LACVD) subsystem in the rectifier and inverter protections and the Commutation Failure Prevention Control (CFPREV) in the inverter protection are activated by default. Restart the simulation.

Notice the 120 Hz oscillations in the DC voltage and currents during the fault. When the fault is cleared at t = 0.8 s, the VDCOL operates and reduces the reference current to 0.3 pu. The system recovers in approximately 0.35 s after fault clearing. The LACVD detects the fault and locks the DC Fault protection that should not detect a DC fault even if the DC line voltage dips. Look at the CFPREV output (A_min_I) which decreases the maximum delay angle limit in order to increase the commutation margin during and after the fault. Now deactivate the CFPREV protection by deselecting the "ON State" in the CFPREV dilaog box. Restart the simulation and observe the difference in recovery time of the DC transmission. Note that a commutation failure now occurs during the recovery. A commutation failure is the result of a failure of the incoming valve to take over the direct current before the commutation voltage reverses its polarity. The symptoms are a zero DC voltage across the affected bridge causing an increase of the DC current at a rate determined mainly by the DC circuit inductance.

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