This is machine translation

Translated by Microsoft
Mouseover text to see original. Click the button below to return to the English version of the page.

Note: This page has been translated by MathWorks. Click here to see
To view all translated materials including this page, select Country from the country navigator on the bottom of this page.


Logic gates for integrated circuits, such as CMOS AND, CMOS OR, CMOS NOT

Simscape Blocks

CMOS ANDModel CMOS AND gate behaviorally
CMOS BufferModel CMOS Buffer gate behaviorally
CMOS NANDModel CMOS NAND gate behaviorally
CMOS NORModel CMOS NOR gate behaviorally
CMOS NOTModel CMOS NOT gate behaviorally
CMOS ORModel CMOS OR gate behaviorally
CMOS XORModel CMOS XOR gate behaviorally
S-R LatchModel an S-R Latch behaviorally
Schmitt TriggerBehavioral model of Schmitt trigger


Parameterizing Blocks from Datasheets

Overview of techniques used to specify block parameters to match the data found on manufacturer datasheets.

Selecting the Output Model for Logic Blocks

Describes the two output models available for logic blocks.