Documentation

Discrete Shift Register

Implement serial-in, parallel-out shift register

Library

Control and Measurements/Additional Components

Description

The Discrete Shift Register block outputs a vector containing the last N samples of the input signal. When the input contains more than one signal, the block outputs the last N samples of each signal in the following order:

Out = [u1(k), u1(k−1), u1(k−2), u1(k−3), u2(k), u2(k−1), u2(k−2), u2(k−3)]

This example shows the block output for an input containing two signals, represented by u1 and u2, and a number of samples N = 4, represented by the k to k−3 indices. The dimension of the output vector is 4 × 2 = 8.

Parameters

Number of samples N

Specify the number of samples, or stages, of the register. The minimum value is 1. Default is 32.

Initial inputs

Specify the initial value of the N-1 samples preceding time 0. Enter a scalar value or a vector of the same size as the input signal. Default is 0.

Sample time

Specify the time interval between the samples. Default is 50e-6.

Characteristics

Direct FeedthroughYes
Sample TimeDiscrete
DimensionalizedYes
Scalar ExpansionYes, of the parameter Initial inputs
Zero-Crossing DetectionNo

Examples

The power_DiscreteShiftRegister example shows various uses of the Discrete Shift Register block.

Introduced in R2013a

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