Modeling a High-Speed Backplane (Part 5: Rational Function to a Verilog-A Module)

This example shows how to use RF Toolbox™ functions to generate a Verilog-A module that models the high-level behavior of a high-speed backplane. First, it reads the single-ended 4-port S-parameters for a differential high-speed backplane and converts them to 2-port differential S-parameters. Then, it computes the transfer function of the differential circuit and fits a rational function to the transfer function. Next, the example exports a Verilog-A module that describes the model. Finally, it plots the unit step response of the generated Verilog-A module in a third-party circuit simulation tool.

Use a Rational Function Object to Describe the High-Level Behavior of a High-Speed Backplane

Read a Touchstone® data file, default.s4pdefault.s4p, into an sparameterssparameters object. The parameters in this data file are the 50-ohm S-parameters of a single-ended 4-port passive circuit, measured at 1496 frequencies ranging from 50 MHz to 15 GHz. Then, extract the single-ended 4-port S-parameters from the data stored in the Parameters property of the sparameters object, use the s2sdds2sdd function to convert them to differential 2-port S-parameters, and use the s2tfs2tf function to compute the transfer function of the differential circuit. Then, use the rationalfitrationalfit function to generate an rfmodel.rationalrfmodel.rational object that describes the high-level behavior of this high-speed backplane. The rfmodel.rational object is a rational function object that expresses the circuit's transfer function in closed form using poles, residues, and other parameters, as described in the rationalfit reference page.

filename = 'default.s4p';
backplane = sparameters(filename);
data = backplane.Parameters;
freq = backplane.Frequencies;
z0 = backplane.Impedance;

Convert to 2-port differential S-parameters.

diffdata = s2sdd(data);
diffz0 = 2*z0;
difftf = s2tf(diffdata,diffz0,diffz0,diffz0);

Fit the differential transfer function into a rational function.

fittol = -30;           % Rational fitting tolerance in dB
delayfactor = 0.9;                % Delay factor
rationalfunc = rationalfit(freq,difftf,fittol,'DelayFactor',delayfactor)
rationalfunc = 

   rfmodel.rational with properties:

        A: [20x1 double]
        C: [20x1 double]
        D: 0
    Delay: 6.0172e-09
     Name: 'Rational Function'

Export the Rational Function Object as a Verilog-A Module

Use the writevawriteva method of the rfmodel.rational object to export the rational function object as a Verilog-A module, called samplepassive1, that describes the rational model. The input and output nets of samplepassive1 are called line_in and line_out. The predefined Verilog-A discipline, electrical, describes the attributes of these nets. The format of numeric values, such as the Laplace transform numerator and denominator coefficients, is %12.10e. The electrical discipline is defined in the file disciplines.vams, which is included in the beginning of the file.

workingdir = tempname;
writeva(rationalfunc, fullfile(workingdir,'samplepassive1'), ...
    'line_in', 'line_out', 'electrical', '%12.10e', 'disciplines.vams');
// Module: samplepassive1

// Generated by MATLAB(R) 8.4 and the RF Toolbox 2.15.

// Generated on: 04-Sep-2014 04:45:09

`include "disciplines.vams"

module samplepassive1(line_in, line_out);
 electrical line_in, line_out;
 electrical node1;

 real nn1[0:1], nn2[0:1], nn3[0:1], nn4[0:1], nn5[0:1], nn6[0:1], nn7[0:1], nn8[0:1], nn9[0:1], nn10[0:0], nn11[0:0];
 real dd1[0:2], dd2[0:2], dd3[0:2], dd4[0:2], dd5[0:2], dd6[0:2], dd7[0:2], dd8[0:2], dd9[0:2], dd10[0:1], dd11[0:1];

 analog begin

   @(initial_step) begin
     nn1[0] = -8.6820751331e+18;
     nn1[1] = -3.0886287871e+08;
     dd1[0] = 1.5798905252e+21;
     dd1[1] = 4.8863990281e+09;
     dd1[2] = 1.0000000000e+00;
     nn2[0] = -4.1968594679e+19;
     nn2[1] = 6.2345632972e+08;
     dd2[0] = 1.1033350108e+21;
     dd2[1] = 6.5450836580e+09;
     dd2[2] = 1.0000000000e+00;
     nn3[0] = 7.2070443279e+19;
     nn3[1] = 5.0284911097e+09;
     dd3[0] = 6.8915848882e+20;
     dd3[1] = 9.7951545058e+09;
     dd3[2] = 1.0000000000e+00;
     nn4[0] = 2.2012066081e+20;
     nn4[1] = -4.5304541584e+09;
     dd4[0] = 3.7125819668e+20;
     dd4[1] = 1.0574962314e+10;
     dd4[2] = 1.0000000000e+00;
     nn5[0] = -2.2648672991e+20;
     nn5[1] = -1.9193261168e+10;
     dd5[0] = 1.8161669182e+20;
     dd5[1] = 1.0007800924e+10;
     dd5[2] = 1.0000000000e+00;
     nn6[0] = -1.3480016767e+17;
     nn6[1] = 1.6320167222e+07;
     dd6[0] = 8.0373440008e+19;
     dd6[1] = 1.1824276827e+09;
     dd6[2] = 1.0000000000e+00;
     nn7[0] = -9.3131801003e+19;
     nn7[1] = 9.8208776253e+09;
     dd7[0] = 5.4036338428e+19;
     dd7[1] = 8.6459656197e+09;
     dd7[2] = 1.0000000000e+00;
     nn8[0] = 6.6496543454e+16;
     nn8[1] = -1.7681089889e+07;
     dd8[0] = 4.3766269685e+19;
     dd8[1] = 7.7289942854e+08;
     dd8[2] = 1.0000000000e+00;
     nn9[0] = 4.5776893633e+14;
     nn9[1] = 1.4933620402e+07;
     dd9[0] = 2.0291494398e+19;
     dd9[1] = 6.0234478052e+08;
     dd9[2] = 1.0000000000e+00;
     nn10[0] = 8.4315444801e+09;
     dd10[0] = 2.7534498777e+09;
     dd10[1] = 1.0000000000e+00;
     nn11[0] = 8.0481323439e+07;
     dd11[0] = 4.7288748225e+08;
     dd11[1] = 1.0000000000e+00;

   V(node1) <+ laplace_nd(V(line_in), nn1, dd1);
   V(node1) <+ laplace_nd(V(line_in), nn2, dd2);
   V(node1) <+ laplace_nd(V(line_in), nn3, dd3);
   V(node1) <+ laplace_nd(V(line_in), nn4, dd4);
   V(node1) <+ laplace_nd(V(line_in), nn5, dd5);
   V(node1) <+ laplace_nd(V(line_in), nn6, dd6);
   V(node1) <+ laplace_nd(V(line_in), nn7, dd7);
   V(node1) <+ laplace_nd(V(line_in), nn8, dd8);
   V(node1) <+ laplace_nd(V(line_in), nn9, dd9);
   V(node1) <+ laplace_nd(V(line_in), nn10, dd10);
   V(node1) <+ laplace_nd(V(line_in), nn11, dd11);
   V(line_out) <+ absdelay(V(node1), 6.0171901584e-09);

Plot the Unit Step Response of the Generated Verilog-A Module

Many third-party circuit simulation tools support the Verilog-A standard. These tools simulate standalone components defined by Verilog-A modules and circuits that contain these components. The following figure shows the unit step response of the samplepassive1 module. The figure was generated with a third-party circuit simulation tool.

Figure 1: The unit step response.

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