# Documentation

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## Export a Verilog-A Model

### Represent a Circuit Object with a Model Object

Before you can write a Verilog-A model of an RF circuit object, you need to create an `rfmodel.rational` object to represent the component.

There are two ways to create an RF model object:

• You can fit a rational function model to the component data using the `rationalfit` function.

• You can use the `rfmodel.rational` constructor to specify the pole-residue representation of the component directly.

This section discusses using a rational function model. For more information on using the constructor, see the `rfmodel.rational` reference page.

When you use the `rationalfit` function to create an `rfmodel.rational` object that represents an RF component, the arguments you specify affect how quickly the resulting Verilog-A model runs in a circuit simulator.

You can use the `rationalfit` function with only the two required arguments. The syntax is:

`model_obj = rationalfit(freq,data)`

where

• `model_obj` is a handle to the rational function model object.

• `freq` is a vector of frequency values that correspond to the data values.

• `data` is a vector that contains the data to fit.

For faster simulation, create a model object with the smallest number of poles required to accurately represent the component. To control the number of poles, use the syntax:

`model_obj = rationalfit(freq,data,tol,weight,delayfactor)`

where

• `tol` — the relative error-fitting tolerance, in decibels. Specify the largest acceptable tolerance for your application. Using tighter tolerance values may force the `rationalfit` function to add more poles to the model to achieve a better fit.

• `weight` — a vector that specifies the weighting of the fit at each frequency.

• `delayfactor` — a value that controls the amount of delay used to fit the data. Delay introduces a phase shift in the frequency domain that may require a large number of poles to fit using a rational function model. When you specify the delay factor, the `rationalfit` function represents the delay as an exponential phase shift. This phase shift allows the function to fit the data using fewer poles.

These arguments are described in detail in the `rationalfit` function reference page.

### Note

You can also specify the number of poles directly using the `npoles` argument. The model accuracy is not guaranteed with approach, so you should not specify `npoles` when accuracy is critical. For more information on the `npoles` argument, see the `rationalfit` reference page.

If you plan to integrate the Verilog-A module into a large design for simulation using detailed models, such as transistor-level circuit models, the simulation time consumed by a Verilog-A module may have a trivial impact on the overall simulation time. In this case, there is no reason to take the time to optimize the rational function model of the component.

For more information on the `rationalfit` function arguments, see the `rationalfit` reference page.

### Write a Verilog-A Module

You use the `writeva` method to create a Verilog-A module that describes the RF model object. This method writes the module to a specified file. Use the syntax:

`status = writeva(model_obj,'obj1',{'inp','inn'},{'outp','outn'})`

to write a Verilog-A module for the model object `model_obj` to the file `obj1.va`. The module has differential input nets, `inp` and `inn`, and differential output nets, `outp` and `outn`. The method returns `status`, a logical value of `true` if the operation is successful and `false` otherwise.

The `writeva` reference page describes the method arguments in detail.

An example of exporting a Verilog-A module appears in the RF Toolbox™ example, Modeling a High-Speed Backplane (Part 5: Rational Function Model to a Verilog-A Module).