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writeva

Write Verilog-A description of rational function object

Syntax

status = writeva(h,filename,innets,outnets, ...
          printformat,discipline,filestoinclude)

Description

status = writeva(h,filename,innets,outnets,printformat, discipline,filestoinclude) writes a Verilog-A module that describes a rational function object h to the file specified by filename. The method implements the object in Verilog-A using Laplace Transform S-domain filters. It returns a status of True, if the operation is successful, and False if it is unsuccessful.

h is the handle to the rational function object. Typically, the rationalfit function creates this object when you fit a rational function to a set of data.

filename is a character vector representing the name of the Verilog-A file to which to write the module. The filename can be specified with or without a path name and extension. The default extension, .va, is added automatically if filename does not end in this extension. The module name that is used in the file is the part of the filename that remains when the path name and extension are removed.

innets is a character vector or a cell array of character vectors that specifies the name of each of the module's input nets. The default is 'in'.

outnets is a character vector or a cell array of character vectors that specifies the name of each of the module's output nets. The default is 'out'.

printformat is a character vector that specifies the precision of the following Verilog-A module parameters using the C language conversion specifications:

  • The numerator and denominator coefficients of the Verilog-A filter.

  • The module's delay value and constant offset (or direct feedthrough), which are taken directly from the rational function object.

The default is '%15.10e'. For more information on how to specify printformat, see the Format specification for fprintf.

discipline specifies the predefined Verilog-A discipline of the nets. The discipline defines attributes and characteristics associated with the nets. The default is 'electrical'.

filestoinclude is a cell array of character vectors that specifies a list of header files to include in the module using Verilog-A '`include' statements. By default, filestoinclude is set to '`include discipline.vams'.

For more information on Verilog-A, use the Verilog-A Reference Manual.

Introduced in R2006b

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