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Executable Specification of a Direct Conversion Receiver

This example shows how to use the RF Blockset™ Circuit Envelope library to simulate the sensitivity performance of a direct conversion architecture with the following RF impairments:

  • Component noise

  • LO-RF isolation

  • Interference from blocker signals

  • Local oscillator phase offset

  • ADC dynamic range

  • Component mismatch

The RF portion of the model includes the explicit specification of gain, noise figure, IP2 and IP3, input\output impedance, and LO phase offset. The transmitter side of the RF interface includes modulation scheme, signal power, and blocker power. The carrier frequencies for the transmitted waveforms are specified in the Inport block. The baseband side includes the number of symbols and full scale range of the ADC.

System Architecture:

This model illustrates the design and simulation of a Direct Conversion ISM Band Receiver. The model is comprised of blocks from RF Blockset, Communications System Toolbox™, DSP System Toolbox™, and Simulink® libraries. The primary subsystems in the model include a digital transmitter, an RF receiver, an ADC, a DC offset correction, and a digital receiver. Blocks and plotted signals are color coded:

  • RF Blockset: Light Blue

  • Communications System Toolbox: Green

  • DSP System Toolbox: Grey

  • Simulink: White

The digital transmitter consists of two 8-PSK modulated waveforms, a target waveform, and an interfering waveform. The waveforms are scaled by 1/sqrt(2) and shifted in frequency for passband-waveform power measurement and spectrum visualization.

The direct-conversion RF receiver has a frequency conversion stage and two gain stages. Resistors model input and output impedances of the RF system as well as the isolation between the LO and RF ports of the mixers. Each of the blocks captures RF impairments relevant to this design. Each of the nonlinear blocks is specified by noise figure. The LNA non-linearity is specified by IP3, and the nonlinearity in the IF amplifiers are specified by both IP2 and IP3. The mixer nonlinearity is specified by IP2. A single LO and a phase shift block provide the cosine and sine terms to the I and Q branches, respectively. To model a thermal noise floor in the RF Blockset environment, the Temperature parameter in the Configuration block specifies a noise temperature of 290.0 K.

The ADC is modeled using an ideal sampler and a N-bit quantizer. The quantizer takes into account the full-scale range of the ADC and the dynamic range. Subsequently, the ADC properly models the system quantization noise floor.

The DC offset correction subsystem contains a Mean block from the DSP System Toolbox library. The block measures the DC offset and subtracts it from the signal. The manual switch in the model enables the user to turn the effect of the offset correction on and off during simulation.

The digital receiver applies a matched filter to the received waveform, implements an AGC function, and demodulates the waveform for symbol-error-rate calculation.

Running the Example

Running the example simulates a design that meets an uncoded 0.5% SER specification. Modifications to the signal power levels and component specifications in the receiver and ADC have a direct impact on the receiver performance. The manual switch in the design enables the user switch the offset correction subsystem in and out to visualize the DC offset effect associated with RF-LO isolation.

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