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Designing a Receiver with an ADC

Most RF receivers in modern communications or radar systems feed signals to an analog-to-digital converter (ADC). Due to their finite resolution, ADCs introduce quantization error into the system. The resolution of the ADC is determined by the number of bits and the full-scale (FS) range of the ADC.

The preceding figure illustrates an RF signal that falls within the dynamic range (DR) of an ADC. The input signal and noise at the carrier fRF has high signal-to-noise ratio (SNR). The received signal at fIF has reduced SNR due to system noise figure. However, if the quantization error is near or above the receiver noise, system performance degrades.

To ensure that the ADC contributes no more than 0.1 dB of noise to the signal at fIF, the quantization noise floor must be 16 dB lower than the receiver noise. This condition can be met by:

  • Reducing the full-scale (FS) range or increasing the resolution of the ADC, which lowers the quantization noise floor.

  • Increasing the gain of the RF receiver, which raises the receiver noise floor.

Overcome Quantization Error of an ADC

The model ex_simrf_adc simulates a low-IF receiver with an ADC. This model is based on the model ex_simrf_snr described in the section Create a Low-IF Receiver Model. At the output of the RF system, the ADC subsystem models an ADC with an FS range of sqrt(100e-3) V and a resolution of 16 bits.

To open this model, at MATLAB® command line, enter:


The power of a voltage signal at the full-scale range of the ADC is

To maximize performance, the model uses the same simulation settings as ex_simrf_snr. To run this model:

  1. Open the model by clicking the link or by typing the model name at the Command Window prompt.

  2. Select Simulation > Run.

View Simulation Output

The model uses subsystems with a MATLAB Coder™ implementation of a fast Fourier transform (FFT) to generate two plots. The FFT uses 64 bins, so for a sampling frequency of 64 Hz, the bandwidth of each bin is 1 Hz. Subsequently, the power levels shown in the figures also represent the power spectral density (PSD) of the signals in dBm/Hz.

  • The Input Display plot shows the power spectrum of the two-tone signal and noise at the input of the receiver-ADC system.

    The measured power of each tone of -142 dBm is consistent with the expected power level of a .1-μV signal. The power level of the noise is consistent with a -174 dBm/Hz noise floor.

  • The Output Display plot shows power spectrum of the output signal.

    The quantization error exceeds the receiver noise.

If you have DSP System Toolbox™ software installed, you can replace the MATLAB Coder subsystems with Vector Scope or Spectrum Analyzer blocks.

Measuring the Quantization Noise Floor

To calculate the quantization noise floor (QNF) of the ADC, subtract the dynamic range from the full-scale power, which is 0 dBm. To calculate the dynamic range PSD for the ADC, use the equation:


  • Nbits is the resolution. The ADC in this example uses 16 bits.

  • Δf is the bandwidth of the FFT, which is 64 in this example. Oversampling in an ADC yields lower quantization noise.

  • The value 1.76 is a correction factor for a pure sinusoidal input.

Therefore, the quantization noise floor is -116 dBm/Hz, in agreement with the measured output levels.

Improving Receiver-ADC Performance

Increasing the gain in the mixer raises the receiver noise without increasing the noise figure. Calculate the mixer gain required to achieve a 16-dB margin between the quantization noise floor and the receiver noise:

To simulate a receiver that clears the quantization noise floor:

  1. Set the Available power gain parameter of the mixer to 23.9.

  2. Select Simulation > Run.

The figure shows that the receiver noise is 16 dB above the quantization noise floor.

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