Documentation

Bus to Vector

Convert virtual bus to vector

  • Library:
  • Simulink / Signal Attributes

Description

The Bus to Vector block converts a virtual bus signal to a vector signal. The input bus signal must consist of scalar, 1-D, or either row or column vectors having the same data type, signal type, and sampling mode. If the input bus contains row or column vectors, this block outputs a row or column vector, respectively; otherwise, it outputs a 1-D array.

Use the block only to replace an implicit bus-to-vector conversion with an equivalent explicit conversion. To identify and correct buses used as vectors without manually inserting Bus to Vector blocks, you can use the Simulink® Model Advisor Check bus signals treated as vectors check. Alternatively, you can use the Simulink.BlockDiagram.addBusToVector function, which automatically inserts Bus to Vector blocks wherever needed.

Note

If you use Save As for a model in a version of the Simulink product before R2007a, Simulink replaces each Bus to Vector block with a null subsystem that outputs nothing. Before you can use the model, reconnect or otherwise correct each signal that used to contain a Bus to Vector block but now is interrupted by a null subsystem.

Ports

Input

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An input virtual bus signal must consist of scalar, 1-D, or either row or column vectors having the same data type, signal type, and sampling mode. If the input is a nonbus signal, the block does no conversion.

Output

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Output a vector signal, based on input bus signal. If the input bus contains row or column vectors, the block outputs a row or column vector, respectively. Otherwise, it outputs a 1-D array.

Parameters

This block has no user-accessible parameters.

Block Characteristics

Data Types

double | single | Boolean | base integer | fixed point | enumerated | bus

Multidimensional Signals

No

Variable-Size Signals

No

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Introduced before R2006a

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