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Check Static Gap

Check that gap exists in signal's range of amplitudes


Model Verification


The Check Static Gap block checks that each element of the input signal is less than (or optionally equal to) a static lower bound or greater than (or optionally equal to) a static upper bound at the current time step. If the verification condition is true, the block does nothing. If not, the block halts the simulation, by default, and displays an error message.

The Check Static Gap block and its companion blocks in the Model Verification library are intended to facilitate creation of self-validating models. For example, you can use model verification blocks to test that signals do not exceed specified limits during simulation. When you are satisfied that a model is correct, you can turn error checking off by disabling the verification blocks. You do not have to physically remove them from the model. If you need to modify a model, you can temporarily turn the verification blocks back on to ensure that your changes do not break the model.

    Note:   For information about how Simulink® Coder™ generated code handles Model Verification blocks, see Debug (Simulink Coder).

Data Type Support

The Check Static Gap block accepts input signals of any dimensions and of any numeric data type that Simulink supports.

For more information, see Data Types Supported by Simulink in the Simulink documentation.


Upper bound

Specify the upper bound of the gap in the input signal's range of amplitudes.

Inclusive upper bound

Selecting this check box specifies that the gap includes the upper bound.

Lower bound

Specify the lower bound of the gap in the input signal's range of amplitudes.

Inclusive lower bound

Selecting this check box specifies that the gap includes the lower bound.

Enable assertion

Clearing this check box disables the Check Static Gap block, that is, causes the model to behave as if the block did not exist. The Model Verification block enabling setting on the All Parameters tab in the Configuration Parameters dialog box allows you to enable or disable all model verification blocks in a model, including Check Static Gap blocks, regardless of the setting of this option.

Simulation callback when assertion fails

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Stop simulation when assertion fails

Selecting this check box causes the Check Static Gap block to halt the simulation when the block's output is zero and the Simulink software displays an error. Otherwise, the Simulink software displays a warning and continues the simulation.

Output assertion signal

Selecting this check box causes the Check Static Gap block to output a Boolean signal that is true (1) at each time step if the assertion succeeds and false (0) if the assertion fails. The data type of the output signal is Boolean if you have selected the Implement logic signals as Boolean data check box on the Optimization pane of the Configuration Parameters dialog box. Otherwise the data type of the output signal is double.

Select icon type

Specify the type of icon used to display this block in a block diagram: either graphic or text. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition. If the icon is too small to display the expression, the text icon displays an exclamation point. To see the expression, enlarge the block.


Data Types

Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated

Sample Time

Inherited from driving block

Direct Feedthrough


Multidimensional Signals


Variable-Size Signals


Zero-Crossing Detection


Code Generation


Introduced before R2006a

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