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Check Static Upper Bound

Check that signal is less than (or optionally equal to) static upper bound

Library

Model Verification

Description

The Check Static Upper Bound block checks that each element of the input signal is less than (or optionally equal to) a specified upper bound at the current time step. Use the block parameter dialog box to specify the value of the upper bound and whether the bound is inclusive. If the verification condition is true, the block does nothing. If not, the block halts the simulation, by default, and displays an error message.

The Check Static Upper Bound block and its companion blocks in the Model Verification library are intended to facilitate creation of self-validating models. For example, you can use model verification blocks to test that signals do not exceed specified limits during simulation. When you are satisfied that a model is correct, you can turn error checking off by disabling the verification blocks. You do not have to physically remove them from the model. If you need to modify a model, you can temporarily turn the verification blocks back on to ensure that your changes do not break the model.

    Note:   For information about how Simulink® Coder™ generated code handles Model Verification blocks, see Debug.

Data Type Support

The Check Static Upper Bound block accepts input signals of any dimensions and of any numeric data type that Simulink supports.

For more information, see Data Types Supported by Simulink in the Simulink documentation.

Parameters and Dialog Box

Upper bound

Specify the upper bound on the range of amplitudes that the input signal can have.

Inclusive boundary

Selecting this check box makes the range of valid input amplitudes include the upper bound.

Enable assertion

Clearing this check box disables the Check Static Upper Bound block, that is, causes the model to behave as if the block did not exist. The Model Verification block enabling setting under Debugging on the Data Validity diagnostics pane of the Configuration Parameters dialog box allows you to enable or disable all model verification blocks in a model, including Check Static Upper Bound blocks, regardless of the setting of this option.

Simulation callback when assertion fails

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Stop simulation when assertion fails

Selecting this check box causes the Check Static Upper Bound block to halt the simulation when the block's output is zero and display an error in the Diagnostic Viewer. Otherwise, the block displays a warning message in the MATLAB Command Window and continues the simulation.

Output assertion signal

Selecting this check box causes the Check Static Upper Bound block to output a Boolean signal that is true (1) at each time step if the assertion succeeds and false (0) if the assertion fails. The data type of the output signal is Boolean if you have selected the Implement logic signals as Boolean data check box on the Optimization pane of the Configuration Parameters dialog box. Otherwise the data type of the output signal is double.

Select icon type

Specify the type of icon used to display this block in a block diagram: either graphic or text. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition. If the icon is too small to display the expression, the text icon displays an exclamation point. To see the expression, enlarge the block.

Characteristics

Direct Feedthrough

No

Sample Time

Inherited from driving block

Scalar Expansion

No

Dimensionalized

Yes

Multidimensionalized

Yes

Zero-Crossing Detection

No

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