Dual Port RAM

Dual port RAM with two output ports

Library

HDL Coder / HDL Operations

Description

The Dual Port RAM block models a RAM that supports simultaneous read and write operations, and has both a read data output port and write data output port. You can use this block to generate HDL code that maps to RAM in most FPGAs.

If you do not need to use the write output data, wr_dout, you can achieve better RAM inference with synthesis tools by using the Simple Dual Port RAM block.

Read-During-Write Behavior

During a write, new data appears at the output of the write port (wr_dout) of the Dual Port RAM block. If a read operation occurs simultaneously at the same address as a write operation, old data appears at the read output port (rd_dout).

Dialog Box and Parameters

Address port width

Address bit width. Minimum bit width is 2, and maximum bit width is 32. The default is 8.

Ports

The block has the following ports:

wr_din

Write data input. The data can be any width. It inherits the width and data type from the input signal.

Data type: scalar fixed point, integer, or complex

wr_addr

Write address.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0

wr_en

Write enable.

Data type: Boolean

rd_addr

Read address.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0

wr_dout

Output data from write address, wr_addr.

rd_dout

Output data from read address, rd_addr.

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