Documentation

Dual Rate Dual Port RAM

Dual Port RAM that supports two rates

Library

HDL Coder / HDL Operations

Description

The Dual Rate Dual Port RAM block models a RAM that supports simultaneous read and write operations to different addresses at two clock rates. Port A of the RAM can run at one rate, and port B can run at a different rate.

In high-performance hardware applications, you can use this block to access the RAM twice per clock cycle. If you generate HDL code, this block maps to a dual-clock dual-port RAM in most FPGAs.

Simultaneous Access

You can access different addresses from ports A and B simultaneously. You can also read the same address from ports A and B simultaneously.

However, do not access an address from one RAM port while it is being written from the other RAM port. During simulation, if you access an address from one RAM port at the same time as you write that address from the other RAM port, the software reports an error.

Read-During-Write Behavior

The RAM has write-first behavior. When you write to the RAM, the new write data is immediately available at the output port.

HDL Code Generation

For simulation results that match the generated HDL code, in the Solver pane of the Configuration Parameters dialog box, clear the checkbox for Treat each discrete rate as a separate task. When the checkbox is cleared, single-tasking mode is enabled.

If you simulate this block with Treat each discrete rate as a separate task selected, multitasking mode is enabled. The output data can update in the same cycle but in the generated HDL code, the output data is updated one cycle later.

Parameters

Address port width

Address bit width. Minimum bit width is 2, and maximum bit width is 28. The default value is 8.

Ports

The block has the following ports:

din_A

Write data input for RAM port A. The data can be any width. It inherits the width and data type from the input signal.

Data type: scalar fixed point, integer, or complex

addr_A

Write address for RAM port A.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0

we_A

Write enable for RAM port A. Set we_A to true for a write operation, or false for a read operation.

Data type: Boolean

din_B

Write data input for RAM port B. The data can be of any width, and inherits the width and data type from the input signal.

Data type: scalar fixed point, integer, or complex

addr_B

Write address for RAM port B.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0

we_B

Write enable for RAM port B. Set we_B to true for a write operation, or false for a read operation.

Data type: Boolean

dout_A

Output data from RAM port A address, addr_A.

dout_B

Output data from RAM port B address, addr_B.

Introduced in R2014a

Was this topic helpful?