HDL FIFO

Stores sequence of input samples in first in, first out (FIFO) register

Library

HDL Coder / HDL Operations

Description

The HDL FIFO block stores a sequence of input samples in a first in, first out (FIFO) register.

Dialog Box and Parameters

Register size

Specify the number of entries that the FIFO register can hold. The minimum is 4. The default is 10.

The ratio of output sample time to input sample time

Inputs (In, Push) and outputs (Out, Pop) can run at different sample times. Enter the ratio of output sample time to input sample time. Use a positive integer or 1/N, where N is a positive integer. The default is 1.

For example:

  • If you enter 2, the output sample time is twice the input sample time, meaning the outputs run slower.

  • If you enter 1/2, the output sample time is half the input sample time, meaning the outputs run faster.

The Full, Empty, and Num signals run at the faster rate.

Push onto full register

Response (Ignore, Error, or Warning) to a trigger received at the Push port when the register is full. The default is Warning.

Pop empty register

Response (Ignore, Error, or Warning) to a trigger received at the Pop port when the register is empty. The default is Warning.

Show empty register indicator port (Empty)

Enable the Empty output port, which is high (1) when the FIFO register is empty and low (0) otherwise.

Show full register indicator port (Full)

Enable the Full output port, which is high (1) when the FIFO register is full and low (0) otherwise.

Show number of register entries port (Num)

Enable the Num output port, which tracks the number of entries currently in the queue.

Ports

The block has the following ports:

In

Data input signal.

Push

Control signal. When this port receives a value of 1, the block pushes the input at the In port onto the end of the FIFO register.

Pop

Control signal. When this port receives a value of 1, the block pops the first element off the FIFO register and holds the Out port at that value.

Out

Data output signal.

Empty

The block asserts this signal when the FIFO register is empty. This port is optional.

Full

The block asserts this signal when the FIFO register is full. This port is optional.

Num

Current number of data values in the FIFO register. This port is optional.

If two or more of the control input ports are triggered in the same time step, the operations execute in the following order:

  1. Pop

  2. Push

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