Single port RAM
HDL Coder / HDL Operations
The Single Port RAM block models RAM that supports sequential read and write operations.
If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM or Simple Dual Port RAM.
Address bit width. Minimum bit width is 2, and maximum bit width is 29. The default is 8.
Controls the output data,
dout, during a
New data (default): During
a write, new data appears at the output port,
Old data: During a write,
old data appears at the output port, dout.
The block has the following ports:
Data input. The data can have any width. It inherits the width and data type from the input signal.
Data type: scalar fixed point, integer, or complex
Data type: scalar unsigned integer (
or unsigned fixed point (
ufixN) with a fraction
Data type: Boolean
Output data from address,