Specify synchronous reset and enable behavior for blocks with state
HDL Coder™ / HDL Subsystems
The State Control block in
improves the HDL simulation behavior of blocks with state, or blocks
that have reset or enable ports. The simulation behavior in
is the same as when you do not add the State Control block
inside the subsystem.
When use the
Synchronous mode of the block,
the Simulink® simulation behavior closely matches that of the
If you have HDL Coder installed, you can generate cleaner
HDL code with the
Synchronous mode of the State
Control block. For more information, see State Control.
Specify whether to use synchronous or classic semantics. The
The following limitations apply to using the State Control block in Simulink. For information about this block in HDL Coder, see State Control in the HDL Coder documentation.
For synchronous semantics in S-function blocks, set
Discrete-Time Integrator blocks with a reset port do not support synchronous semantics.
The following blocks are not allowed in synchronous mode:
Continuous time blocks and blocks with continuous rate
Simulink blocks with Input processing set
Columns as channels (frame based), where
this parameter applies.
From Workspace block
The set of unit delay blocks in the Additional Math & Discrete > Additional Discrete sublibrary in Simulink, such as the Unit Delay Resettable and Unit Delay External IC blocks
Conditional subsystems using classic semantics cannot have subsystems with synchronous semantics inside them.
Conditional subsystems must be single rate when you use the State Control block in synchronous mode.
Synchronous Enabled Subsystem cannot contain reset subsystems or a reset parameter port. For example, you cannot have a Delay block with an external reset port inside the subsystem.
These blocks are not supported in synchronous mode:
Variable-size signals are not supported with synchronous semantics.
Synchronous semantics do not propagate across model
boundaries. If your parent model has synchronous semantics, any referenced
model must have synchronous semantics explicitly specified. At the
root level of each referenced model, add a State Control block
with the State control parameter set to