Documentation

Unit Delay Enabled Synchronous

Delay input signal by one sample period when external Enable signal is true

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  • HDL Coder / Discrete / Unit Delay Enabled Synchronous

Description

The Unit Delay Enabled Synchronous block delays the input signal u by one sample period when the external Enable signal is true. When the Enable signal is false, the state and output signal hold the previous value. The Enable signal is true when E is not zero and false when E is zero.

The Unit Delay Enabled Synchronous block implementation consists of a Synchronous Subsystem that contains an Enabled Delay block with a Delay length of one and a State Control block in Synchronous mode. When you use this block in your model and haveHDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware resources due to the Synchronous behavior of the State Control block.

Limitations

  • The block does not support vector inputs on the Enable port.

  • You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that use Classic semantics. The Subsystem must use Synchronous semantics.

Ports

Input

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The Unit Delay Enabled Synchronous block accepts the input signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated | bus

Input

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The Unit Delay Enabled Synchronous block accepts the Enable signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Output

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Output data type always matches input.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated | bus

Parameters

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The Initial condition can take a scalar input or use the same data type as the input signal. You cannot run the simulation with NaN or Inf as the Initial condition.

Programmatic Use

Block parameter: InitialCondition
Type: character vector
Value: '0' | '[n]' | '[m n]'
Default: '0'

The Sample time must be a real double scalar that specifies the period or a real double vector of length two that specifies the period and offset. The period and offset must be finte and non-negative with offset less than the period.

Programmatic Use

Block parameter: SampleTime
Type: character vector
Value: '-1' | '[n]' | '[m n]'
Default: '-1'

Block Characteristics

Data Types

double | single | base integer | fixed point | bus

Sample Time

Inherit

Direct Feedthrough

Yes

Multidimensional Signals

Scalar

Variable-Size Signals

Yes

Zero-Crossing Detection

No

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point algorithms using Fixed-Point Designer™.

Introduced in R2017b

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