Delay signal one sample period, with external Boolean reset
The Unit Delay Resettable block delays a signal one sample period.
The block can reset both its state and output based on an external reset signal R. The block has two input ports, one for the input signal u and the other for the external reset signal R.
At the start of simulation, the block's Initial condition parameter determines its initial output. During simulation, when the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state and its output to the Initial condition.
You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.
The Unit Delay Resettable block accepts signals of the following data types:
The output has the same data type as the input u. For enumerated signals, the Initial condition must be of the same enumerated type as the input u.
For more information, see Data Types Supported by Simulink in the Simulink® documentation.
Specify the initial output of the simulation.
Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.
No, of the input port
Yes, of the reset port
Specified in the Sample time parameter
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