Delay signal one sample period, with external Boolean reset and initial condition
The Unit Delay Resettable External IC block delays a signal one sample period.
The block can reset its state based on an external reset signal R. The block has two input ports, one for the input signal u and the other for the reset signal R. When the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state to the initial condition given by the signal IC and outputs that state delayed by one time step.
You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.
The Unit Delay Resettable External IC block accepts signals of the following data types:
The data types of the inputs u and IC must be the same. The output has the same data type as u and IC.
For more information, see Data Types Supported by Simulink in the Simulink® documentation.
Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.
No, of the input port
Yes, of the reset port
Yes, of the external IC port
Specified in the Sample time parameter
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