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Designing a Simulink PID Controller (2DOF) Block for a Reactor

This example shows how to use PID Tuner to tune a Simulink PID Controller (2DOF) block.

Introduction of the PID Controller (2DOF) Block

With a 2DOF PID controller, also known as ISA-PID controller, you can achieve good performance for both reference tracking and disturbance rejection. It contains a standard PID controller in the feedback loop and adds a pre-filter to the reference signal. The pre-filter helps produce a smoother transient response to set-point changes. In this example, you use a Simulink PID Controller (2DOF) block to control a continuous stirred tank reactor (CSTR) and you design this 2DOF PID controller in the PID Tuner.

A typical design workflow with the PID Tuner involves the following tasks:

(1) Launch the PID Tuner. When launching, the software automatically computes a linear plant model from the Simulink model and designs an initial controller.

(2) Tune the controller in the PID Tuner by manually adjusting design criteria in two design modes. The tuner computes PID parameters that robustly stabilize the system.

(3) Export the parameters of the designed controller back to the PID Controller block and verify controller performance in Simulink.

Opening the Model

Open the CSTR control model and take a few moments to explore it.

open_system('scdcstrctrlpidblock');

The CSTR plant is initialized at an equilibrium operating point. The nominal value of the residual concentration is 1.96 mol/L, which is the initial condition of the Residual Concentration Reference block and the Integrator1 block in the CSTR subsystem.

The initial condition of the integrator I0 in the PID controller block is determined by the equilibrium operating point. In this example, since we have a PI controller in parallel form,

   I0 = u0 - ((b-1)*y0*P)

where u0 is the steady state controller output (300), and y0 is the steady state plant output (1.96). Since b is 1, I0 = u0 = 300.

For background, see Seborg, D.E. et al., "Process Dynamics and Control", 2nd Ed., 2004, Wiley, pp.34-36.

Design Overview

In this example, control the residual concentration of the CSTR by manipulating reactor coolant temperature. The overall design requirements are:

  • Track a sudden decrease of 0.5 in the reference signal from a Simulink step block Residual Concentration Reference. The detailed design requirements are:

         Settling time under 10 seconds
         Zero steady-state error to the step reference input
         Overshoot below 0.1
  • Reject a 5 degree sudden increase in the feed temperature from a Simulink step block Feed Temperature. The detailed design requirements are:

         Settling time under 10 seconds
         Peak deviation from steady state below 0.01

In this example you design a PI controller in the PID Tuner to achieve good responses in both reference tracking and disturbance rejection.

Opening the PID Tuner

To launch the PID Tuner, double-click the PID Controller block to open its block dialog. In the Main tab, click Tune.

After you launch the PID Tuner, close the PID block dialog and move the PID Tuner beside the Simulink model. Also, open the residual concentration scope window.

Initial PID Design

When the PID Tuner launches, the software computes a linearized plant model. The software automatically identifies the plant input and output, and uses the current operating point for the linearization. The plant can have any order and can have time delays.

The PID Tuner computes an initial PI controller to achieve a reasonable tradeoff between performance and robustness. By default, step reference tracking performance displays in the plot.

Click Show parameters to view controller parameters P, I, b, and a set of performance and robustness measurements. In this example, the initial PI controller design gives a settling time of 4.4 second, which meets the requirement.

The following figure shows the PID Tuner dialog with initial design:

To test the initial design on the nonlinear model, click Update Block in the PID Tuner. This writes the parameters back to the PID block in the Simulink model. Run a simulation and view the closed-loop response:

The transient response of disturbance rejection shows that its peak deviation is about 0.2, which exceeds the design requirement. You need to reduce the peak deviation by at least 50% using the PID Tuner.

Design for Disturbance Rejection in the Time Domain Design Mode

The PID Tuner provides step plot for different loop responses such as reference tracking (from r to y) and controller efforts (from r to u), etc. In this example since the disturbance occurs at the reactor feed temperature, the closest plot you can get is the input disturbance rejection plot that assumes a step disturbance occurs at the input of the plant model.

Click Add Plot, select Input disturbance rejection and click Add to create an input disturbance plot. The plot shows the disturbance rejection performance with initial controller:

You need to reduce the peak deviation from -0.02 to -0.01 while maintaining a settling time less than 10 seconds. First, try to reduce the peak deviation by decreasing the response time, which can be achieved by moving the response time slider to the right.

The following figure shows the peak deviation is less than 0.01 when response time is reduced to 0.6 second:

But the settling time now significantly exceeds 10 seconds. To reduce the settling time below 10 seconds, you also need to make the transient behave more aggressively, which can be achieved by moving the transient behavior slider to the left.

The following figure shows the final disturbance rejection performance when the response time is 0.6 seconds and the transient behavior value is 0.25.

To test the new design on the nonlinear model, click Update Block in the PID Tuner. Run a simulation and view the closed-loop response:

The disturbance rejection performance satisfies the requirements. However, because the controller is very aggressive, the overshoot of reference tracking now exceeds the limit as shown in the figure below.

You need to adjust the pre-filter in the 2DOF PID block to improve the reference tracking performance.

Completing PID Design with Set-point Weighting

The parameter b in an ISA PI or PID controller is the set-point weight on the reference signal feeding into the proportional gain of the controller. It has a range between 0 and 1, and its default value is 1. By reducing its value, the reference tracking performance becomes smoother. In this example, open the PID block dialog and set b to 0.

Because b and P are changed, you need to adjust the initial condition of the integrator I0 in the PID controller block to make sure the initial operating point is still at equilibrium. The relationship is:

   I0 = u0 - ((b-1)*y0*P)

where u0 is 300 and y0 is 1.96. With P from PID Tuner (-107) and b from the block dialog (0), I0 becomes 90. Update the initial condition of the integrator with this value in the block dialog and the simulation will start at the equilibrium operating point.

The following figure shows that there is no overshoot in reference tracking with the updated design.

In summary, you can design a 2DOF PID controller in two steps to achieve balanced performance in reference tracking and disturbance rejection. The first step is using the PID Tuner to obtain good load disturbance rejection; and the second step is manually adjusting set-point weights b and c in the block dialog to obtain good reference tracking. Notice that changing b and c does not affect closed-loop stability or load disturbance rejection performance.

bdclose('scdcstrctrlpidblock')
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