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Assess Simulation Using Logical Statements

A verify statement sends results to the Test Manager and allows simulation to run even when the logical condition fails. An assert statement stops simulation. You can use verify and assert statements to assess your model.

verify

The verify keyword assesses a logical expression inside a Test Sequence or Test Assessment block. Optional arguments label results in the Test Manager and diagnostic viewer. The keyword and arguments constitute a verify statement. Use the logical expression to define a verification constraint on the system under test.

For each simulation step, the verify statement reports whether the logical expression fails, passes, or is untested. For an overall test, a verify statement returns an overall fail, pass, or untested result. Any failure at a simulation step results in an overall failure. If the verify statement does not fail, and at any simulation time step the statement passes, the overall result passes. Otherwise, the statement is not tested, and the overall result is untested. Review results in the Verify Statements section of the Test Manager.

Syntax

A verify statement uses syntax of these forms

verify(expression)
verify(expression,errorMessage)
verify(expression,identifier,errorMessage)

The simplest verify statement uses only a logical expression. To make results easier to interpret, use additional arguments to define an error message and a statement identifier. Error messages display in the diagnostic viewer. You can use error messages to display key values at the time the statement fails.

For example, if verify evaluates an expression containing variables x and y, you can display the values of x and y using the string:

'x and y values are %d, %d',x,y

An identifier labels the verify results in the Test Manager. The identifier uses a string of the form 'prefix:suffix'. prefix and suffix are alphanumeric strings. For example:

'SimulinkTest:x_equals_y'

Continuous-Time Considerations

verify is not supported in Test Sequence blocks that use continuous-time updating. Test Sequence block data can depend on factors such as the solver step time. Continuous-time updating can cause differences in when block data and verify statements update, which can lead to unexpected verify statement results.

If your model uses continuous time and you use verify statements in a Test Sequence or Test Assessment block, consider explicitly setting a discrete block sample time.

Example

In this comparison of two values, the parent step uses verify statements to assess two local variables x and y during the simulation. The substeps set two conditions.

  • verify(x >= y) passes overall because it is true for the entire test sequence.

  • verify(x == y) and verify(x ~= y) fail because they fail in step_1_2 and step_1_1, respectively.

The Test Manager displays the results.

assert

assert evaluates a logical argument, but unlike verify, assert stops simulation. assert does not return fail, pass, or untested results. Failures appear as errors. Consider using assert statements to avoid executing a bad test. For example, if a component under test outputs two signals h and k, and the test requires h and k initialized to 0, use assert to stop the test if the signals do not initialize.

To make results easier to interpret, add an optional message that evaluates when the assertion fails. This example demonstrates an assert statement that returns a message if the logical condition fails.

Code is not generated for assert statements in the Test Sequence block.

Assessment Statements

To verify simulation, stop simulation, and return verification results, use assessment statements.

KeywordStatement SyntaxDescriptionExample
verify

verify(expression)

verify(expression, errorMessage)

verify(expression, identifier, errorMessage)

Assesses a logical expression. Optional arguments label results in the Test Manager and diagnostic viewer.

verify(x > y,...
'SimulinkTest:greaterThan',...
'x and y values are %d, %d',x,y)
assert

assert(expression)

assert(expression, errorMessage)

Evaluates a logical expression. Failure stops simulation and returns an error. Optional arguments return an error message.

assert(h == 0 && k == 0,...
'h and k must initialize to 0')

Syntax in the table uses these arguments:

 expression

 identifier

 errorMessage

Logical Operators

You can use logical connectives in actions, transitions, and assessments. In these examples, p and q represent Boolean signals or logical expressions.

OperationSyntaxDescriptionExample

Negation

~p

not p

verify(~p)

Conjunction

p && q

p and q

verify(p && q)

Disjunction

p || q

p or q

verify(p || q)

Implication

~p || q

if p, q. Logically equivalent to implication pq.

verify(~p || q)

Biconditional

(p && q) || (~p && ~q)

p and q, or not p and not q. Logically equivalent to biconditional pq.

verify((p && q) || (~p && ~q))

Relational Operators

You can use relational operators in actions, transitions, and assessments. In these examples, x and y represent numeric-type variables.

Using == or ~= operators in a verify statement returns a warning when comparing floating-point data. Consider the precision limitations associated with floating-point numbers when implementing verify statements. See Floating-Point Numbers (MATLAB). If you use floating-point data, consider defining a tolerance for the assessment. For example, instead of verify(x == 5), verify x within a tolerance of 0.001:

verify(abs(x-5) < 0.001)

Operator and SyntaxDescriptionExample
x > yGreater thanverify(x > y)
x < yLess thanverify(x < y)
x >= yGreater than or equal toverify(x >= y)
x <= yLess than or equal toverify(x <= y)
x == yEqual toverify(x == y)
x ~= yNot equal toverify(x ~= y)

See Also

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