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SIL Verification for a Subsystem

This example shows subsystem verification by ensuring the output of software-in-the-loop (SIL) code matches that of the model subsystem. You generate a SIL verification harness, collect simulation results, and compare the results using the simulation data inspector. You can apply a similar process for processor-in-the-loop (PIL) verification.

With SIL simulation, you can verify the behavior of production source code on your host computer. Additionally, with PIL simulation, you can verify the compiled object code that you intend to deploy in production. You can run the PIL object code on real target hardware or on an instruction set simulator.

If you have an Embedded Coder® license, you can create a test harness in SIL or PIL mode for model verification. You can compare the SIL or PIL block results with the model results and collect metrics, including execution time and code coverage. Using the test harness to perform SIL and PIL verification, you can:

  • Manage the harness with your model. Generating the test harness generates the SIL block. The test harness is associated with the component under verification. You can save the test harness with the main model.

  • Use built-in tools for these test-design-test workflows:

    • Checking the SIL or PIL block equivalence

    • Updating the SIL or PIL block to the latest model design

  • View and compare logged data and signals using the Test Manager and Simulation Data Inspector.

For information about running multiple simulations with unchanged generated code, see .

Also see Code Generation of Subsystems (Simulink Coder).

The example models a closed-loop controller-plant system. The controller regulates the plant output.

Create a SIL Verification Harness for a Controller

Create a SIL verification harness using data that you log from a controller subsystem model simulation. You need an Embedded Coder license for this example.

  1. Open the example model by entering

    rtwdemo_sil_block
    at the MATLAB® command prompt,

  2. Save a copy of the model using the name controller_model in a new folder, in a writable location on the MATLAB path.

  3. Enable signal logging for the model. At the command prompt, enter

    set_param(bdroot,'SignalLogging','on','SignalLoggingName',...
    'SIL_signals','SignalLoggingSaveFormat','Dataset')
  4. Right-click the signal into Controller port In1, and select Properties. In the Signal Properties dialog box, for the Signal name, enter controller_model_input. Select Log signal data and click OK.

  5. Right-click the signal out of Controller port Out1, and select Properties. In the Signal Properties dialog box, for the Signal name, enter controller_model_output. Select Log signal data and click OK.

  6. Simulate the model.

  7. Get the logged signals from the simulation output into the workspace. At the command prompt, enter

    out_data = out.get('SIL_signals');
    control_in1 = out_data.get('controller_model_input');
    control_out1 = out_data.get('controller_model_output');
  8. Create the software-in-the-loop test harness. Right-click the Controller subsystem and select Test Harness > Create Test Harness (Controller).

  9. Set the harness properties:

    • Name: SIL_harness

    • Sources and Sinks: Inport and Outport

    • Initial harness configuration: Verification

    • Verification Mode: Software-in-the-loop (SIL)

    • Select Open harness after creation

    Click OK. The resulting test harness has a SIL block.

Configure and Simulate a SIL Verification Harness

Configure and simulate a SIL verification harness for a controller subsystem.

  1. Configure the test harness to import the logged controller input values. From the top level of the test harness, in the model Configuration Parameters dialog box, in the Data Import/Export pane, select Input. Enter control_in1.Values as the input and click OK.

  2. Enable signal logging for the test harness. At the command prompt, enter

    set_param('SIL_harness','SignalLogging','on','SignalLoggingName',...
    'harness_signals','SignalLoggingSaveFormat','Dataset')
  3. Right-click the output signal of the SIL block and select Properties. In the Signal Properties dialog box, for the Signal name, enter SIL_block_out. Select Log signal data and click OK.

  4. Simulate the harness.

Compare the SIL Block and Model Controller Outputs

Compare the outputs for a verification harness and a controller subsystem.

  1. In the test harness model, click the Simulation Data Inspector button to open the Simulation Data Inspector.

  2. In the Simulation Data Inspector, click Import. In the Import dialog box.

    • Set Import from to: Base workspace.

    • Set Import to to: New Run.

    • Under Data to import, select Signal Name to import data from all sources.

  3. Click Import.

  4. Select the SIL_block_out and controller_model_out signals in the Runs pane of the data inspector window.

    The chart displays the two signals, which overlap. This result suggests equivalence for the SIL code. You can plot signal differences using the Compare tab in SDI, and perform more detailed analyses for verification. For more information, see Compare Simulation Data (Simulink).

  5. Close the test harness window. You return to the main model. The badge on the Controller block indicates that the SIL harness is associated with the subsystem.

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