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Create a Simulink® model that you can use to examine the Verification Manager.
In the example model, the contents of the subsystem are as follows.
In the Signal Builder block, create a signal group with five signals in the group.
Make two copies of the signal group, so that you have three signal groups: Group 1, Group 2, Group 3.
Note: A Signal Builder block provides test signals for an entire model from one location. This model contains a Signal Builder block that feeds five test signals to the Model Verification blocks. The model sends the first four signals directly to Check Static Upper Bound blocks. The model sends the fifth signal to a subsystem that contains a Check Static Upper Bound block.
For more information on the Signal Builder block, see Signal Groups in the Simulink documentation.
To set each Check Static Upper Bound verification block to assert for an upper bound of 1, set the Upper bound parameter to 1.
For the following blocks, disable the assertion by clearing the Enable assertion parameter:
Check Static Upper Bound
Check Static Upper Bound1
Check Static Upper Bound2
Check Static Upper Bound in the subsystem
These blocks are crossed out in the model.
To enable the Check Static Upper Bound3 block, select the Enable assertion parameter.
Save this model and name it ex_verif_mgr_test_signals.
The Verification block settings pane and the Requirements pane are displayed.
The Verification block settings pane lists all Model Verification blocks in the model, grouped by subsystem. If you right-click in this pane, you can select on of three options for viewing Model Verification blocks in this window:
Display > Tree format — If enabled, lists the blocks as they appear in the model hierarchy.
Display > Overridden blocks only — If enabled, lists only the blocks that have been disabled.
Display > Active blocks only — If enabled, lists only the blocks that are enabled.
Note: If both Overridden blocks only and Active blocks only are enabled, no Model Verification blocks appear. If both Overridden blocks only and Active blocks only are disabled, all Model Verification blocks appear.
In this example, the Verification block settings pane displays five Check Static Upper Bound blocks. Four are in the top level of the model, and one is in a subsystem.
The Requirements pane lists the requirements document links for the current signal group. For details on adding requirement document links in the Signal Builder dialog box, see Link Test Cases to Requirements Documents Using the Verification Manager.
The Verification block settings pane lists the Model Verification blocks in the model. Each verification block has a status node that indicates whether its assertion is enabled or disabled. Each verification block's status node also indicates whether the enabled or disabled setting applies universally or to the active group. The following table describes the different types of status nodes.
Verification block is disabled for this group. Click to enable for the current group.
Verification block is enabled for the current group. Click to disable for the current group.
Verification block is enabled for all test groups.
Use the Verification Manager to enable or disable model verification blocks in the ex_verif_mgr_test_signals model that you created in View Model Verification Blocks.
Because you enabled the Check Static Upper Bound1 block in the current group, an Override label is applied to the block and it is no longer crossed out.
Select the empty check box next to the Check Static Upper Bound2 node to enable that block for the current group (Group 2).
The Check Static Upper Bound2 block is no longer crossed out, indicating that the block is enabled for the current group. Check Static Upper Bound1, however, is crossed out because it is enabled in a different group.
Save the model with these changes.
If you have a lot of verification blocks, it is tedious to enable and disable blocks individually. Using the Verification Manager, you can enable and disable blocks from context menu options. Depending on the status of the node, you have the following options.
Context Menu Options
For example, assume that you define the following groups in the Verification Manager for a model with five Model Verification blocks.
This option enables all verification blocks, for all test groups, in all subsystems; the settings for all groups look as follows:
This option restores the individually enabled/disabled settings for each verification block in each group.
This option individually enables all contained blocks for only Group 1.
This option individually disables all contained blocks for only Group 1.
This option enables the Check Static Upper Bound block for all groups.
This option restores the individually enabled/disabled state to this block for all groups. The Block enable by group option lets you enable or disable this node individually for each group.
This option enables the Check Static Upper Bound block for this group only.
Selecting Block group disable disables the specified block for this group only.
The following example uses a Check Static Lower Bound block to stop simulation when a signal from a Sine Wave block crosses its lower bound limit.
Attach a Check Static Lower Bound block to the signal from a Sine Wave block.
Set the Simulation stop time to 2 seconds.
Double-click the Sine Wave block and set the following parameters:
Set the Amplitude to 1.
Set the Frequency to pi radians per second.
Enable assertion is the default. This parameter enables a verification block for an assertion. You set the Check Static Lower Bound block to detect a signal value of –0.8 or lower. If the signal value reaches that value or falls below it, the simulation stops.
Run the simulation.
The model stops simulating after 1.295 seconds, when the output is –0.8. The software highlights the Check Static Lower Bound block.
To verify the signal value, double-click the Scope block.
To disable the Check Static Lower Bound block from asserting its limit, clear the Enable assertion check box.
The block is crossed out in the model, as shown.
You can link requirements documents to test cases and their corresponding Model Verification blocks through the Verification Manager Requirements pane in the Signal Builder.
To display the Requirements pane in the Signal Builder dialog box:
Click the Show verification settings button ( ).
Click the Requirements display button ( ).
The Requirements dialog box opens.
When you browse and select a requirements document, the RMI stores the document path as specified by the Document file reference option on the Requirements Settings dialog box, Selection Linking tab.
For information about which setting to use for your working environment, see Document Path Storage.
Add links to requirements documents, as described in Link to Requirements Document Using Selection-Based Linking.
The names of the linked requirements appear in the Requirements pane.