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Construct Simulation Tests Using the Verification Manager

Model Verification Blocks and the Verification Manager

Simulink® Model Verification library blocks monitor time-domain signals in your model during simulation, according to the specifications that you assign to the blocks.

    Note:   To see a complete description of all Simulink model verification blocks, see the Model Verification (Simulink) category.

You set a verification block to assert when its signal leaves the limit or range that you specify. During simulation, when the signal crosses the limit, the verification block can:

  • Stop the simulation and bring immediate focus to that part of the model.

  • Report the limit encounter with a logical signal output of its own. If the simulation does not encounter the limit, the signal output is true. If the simulation encounters the limit, the signal output is false.

The Verification Manager is a graphical interface in the Signal Builder dialog box. Using this tool, you can manage all the Model Verification blocks in your model from a central location.

If you have Simulink Control Design™ software, you can also monitor frequency-domain characteristics such as:

  • Gain and phase margins

  • Peak magnitude

    Note:   For more information about the Simulink Control Design model verification blocks, see Model Verification (Simulink Control Design).

View Model Verification Blocks

Create a Simulink model that you can use to examine the Verification Manager.

  1. In the Simulink software, create the following example model.

    In the example model, the contents of the subsystem are as follows.

    1. In the Signal Builder block, create a signal group with five signals in the group.

    2. Make two copies of the signal group, so that you have three signal groups: Group 1, Group 2, Group 3.

        Note:   A Signal Builder block provides test signals for an entire model from one location. This model contains a Signal Builder block that feeds five test signals to the Model Verification blocks. The model sends the first four signals directly to Check Static Upper Bound blocks. The model sends the fifth signal to a subsystem that contains a Check Static Upper Bound block.

      For more information on the Signal Builder block, see Signal Groups (Simulink).

    3. To set each Check Static Upper Bound verification block to assert for an upper bound of 1, set the Upper bound parameter to 1.

    4. For the following blocks, disable the assertion by clearing the Enable assertion parameter:

      • Check Static Upper Bound

      • Check Static Upper Bound1

      • Check Static Upper Bound2

      • Check Static Upper Bound in the subsystem

      These blocks are crossed out in the model.

    5. To enable the Check Static Upper Bound3 block, select the Enable assertion parameter.

  2. Save this model and name it ex_verif_mgr_test_signals.

  3. To open the model Signal Builder dialog box, double-click the Signal Builder block. The signals in the first group (Group 1 in this example) are displayed.

  4. On the Signal Builder dialog box toolbar, select the Show Verification Settings tool .

    The Verification block settings pane and the Requirements pane are displayed.

    The Verification block settings pane lists all Model Verification blocks in the model, grouped by subsystem. If you right-click in this pane, you can select on of three options for viewing Model Verification blocks in this window:

    • Display > Tree format — If enabled, lists the blocks as they appear in the model hierarchy.

    • Display > Overridden blocks only — If enabled, lists only the blocks that have been disabled.

    • Display > Active blocks only — If enabled, lists only the blocks that are enabled.

      Note:   If both Overridden blocks only and Active blocks only are enabled, no Model Verification blocks appear. If both Overridden blocks only and Active blocks only are disabled, all Model Verification blocks appear.

    In this example, the Verification block settings pane displays five Check Static Upper Bound blocks. Four are in the top level of the model, and one is in a subsystem.

    The Requirements pane lists the requirements document links for the current signal group. For details on adding requirement document links in the Signal Builder dialog box, see Link Test Cases to Requirements Documents Using the Verification Manager.

  5. For this example, select to close the Requirements pane.

  6. To display only the enabled Model Verification blocks for the current signal group, in the Verification block settings toolbar, select the List Enabled Verifications tool .

  7. To redisplay all Model Verification blocks for the current group, click the Show Verification Block Hierarchy tool .

Enable and Disable Model Verification Blocks in a Model

Use the Verification Manager to enable and disable individual Model Verification blocks in signal groups. To open the Verification Manager in the Signal Builder dialog box, click .

The Verification block settings pane lists the Model Verification blocks in the model. Each verification block has a status node that indicates whether its assertion is enabled or disabled. Each verification block's status node also indicates whether the enabled or disabled setting applies universally or to the active group. The following table describes the different types of status nodes.

Node

Status

Verification block is disabled for this group. Click to enable for the current group.

Verification block is enabled for the current group. Click to disable for the current group.

Verification block is enabled for all test groups.

Use the Verification Manager to enable or disable model verification blocks in the ex_verif_mgr_test_signals model that you created in View Model Verification Blocks.

  1. In the Verification Manager, click the empty check box next to the Check Static Upper Bound1 node to enable that node for the current active group (Group 1).

    In the Verification block settings pane, when you enable a disabled block, you see the following change in how the block is displayed in the model.

    Because you enabled the Check Static Upper Bound1 block in the current group, an Override label is applied to the block and it is no longer crossed out.

  2. In the Signal Builder, from the Active Group list, select Group 2.

  3. Select the empty check box next to the Check Static Upper Bound2 node to enable that block for the current group (Group 2).

    The Check Static Upper Bound2 block is no longer crossed out, indicating that the block is enabled for the current group. Check Static Upper Bound1, however, is crossed out because it is enabled in a different group.

  4. Save the model with these changes.

Enable and Disable Model Verification Blocks in a Subsystem

If you have a lot of verification blocks, it is tedious to enable and disable blocks individually. Using the Verification Manager, you can enable and disable blocks from context menu options. Depending on the status of the node, you have the following options.

Node Status

Context Menu Options

  • Contents enable for all groups

  • Contents enable by group

  • Contents group enable

  • Contents group disable

  • Block enable by group

  • Block enable for all groups

  • Block group enable

  • Block enable for all groups

  • Block group disable

For example, assume that you define the following groups in the Verification Manager for a model with five Model Verification blocks.

  1. In the Verification Manager window, right-click the ex_verif_mgr_test_signals node and select Contents enable for all groups.

    This option enables all verification blocks, for all test groups, in all subsystems; the settings for all groups look as follows:

  2. Right-click ex_verif_mgr_test_signals and select Contents enable by group.

    This option restores the individually enabled/disabled settings for each verification block in each group.

  3. From the Active Group list, select Group 1. Right-click ex_verif_mgr_test_signals, and select Contents group enable.

    This option individually enables all contained blocks for only Group 1.

  4. From the Active Group list, select Group 1. Right-click ex_verif_mgr_test_signals and select Contents group disable.

    This option individually disables all contained blocks for only Group 1.

  5. From the Active Group list, select Group 1. Right-click the Check Static Upper Bound node, and select Block enable for all groups.

    This option enables the Check Static Upper Bound block for all groups.

  6. From the Active Group list, select Group 1. Right-click the Check Static Upper Bound node, and select Block enable by group.

    This option restores the individually enabled/disabled state to this block for all groups. The Block enable by group option lets you enable or disable this node individually for each group.

  7. From the Active Group list, select Group 1. Right-click the Check Static Upper Bound node, and select Block group enable.

    This option enables the Check Static Upper Bound block for this group only.

    Selecting Block group disable disables the specified block for this group only.

Use Check Static Lower Bound Block to Check for Out-of-Bounds Signal

The following example uses a Check Static Lower Bound block to stop simulation when a signal from a Sine Wave block crosses its lower bound limit.

  1. Attach a Check Static Lower Bound block to the signal from a Sine Wave block.

  2. Set the Simulation stop time to 2 seconds.

  3. Double-click the Sine Wave block and set the following parameters:

    • Set the Amplitude to 1.

    • Set the Frequency to pi radians per second.

  4. Double-click the Check Static Lower Bound block and set the Lower bound parameter to -0.8.

    Enable assertion is the default. This parameter enables a verification block for an assertion. You set the Check Static Lower Bound block to detect a signal value of –0.8 or lower. If the signal value reaches that value or falls below it, the simulation stops.

  5. Run the simulation.

    The model stops simulating after 1.295 seconds, when the output is –0.8. The software highlights the Check Static Lower Bound block.

    When the simulation stops, you see the following diagnostic message.

  6. To verify the signal value, double-click the Scope block.

  7. To disable the Check Static Lower Bound block from asserting its limit, clear the Enable assertion check box.

    The block is crossed out in the model, as shown.

Link Test Cases to Requirements Documents Using the Verification Manager

You can link requirements documents to test cases and their corresponding Model Verification blocks through the Verification Manager Requirements pane in the Signal Builder.

  1. To display the Requirements pane in the Signal Builder dialog box:

    1. Click the Show verification settings button ( ).

    2. Click the Requirements display button ( ).

  2. In the Requirements pane, right-click anywhere.

  3. From the context menu, select Link Editor.

    The Requirements dialog box opens.

  4. When you browse and select a requirements document, the RMI stores the document path as specified by the Document file reference option on the Requirements Settings dialog box, Selection Linking tab.

    For information about which setting to use for your working environment, see Document Path Storage.

  5. Add links to requirements documents, as described in Link to Requirements Document Using Selection-Based Linking.

    The names of the linked requirements appear in the Requirements pane.

  6. To view the requirements document in its native editor, right-click a requirement link and select View.

  7. Optionally, to delete a requirement link, right-click the link and select Delete.

Linear System Modeling Blocks in Simulink Control Design

If you have Simulink Control Design software, you can:

  • Specify bounds on linear system characteristics.

  • Check that the bounds are satisfied during simulation.

For example, you can check if the linearized behavior of your model satisfied upper and lower magnitude bounds on a Bode plot or gain and phase margins. For more information, see the individual block reference pages in Model Verification (Simulink Control Design).

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