Describes three design patterns for scheduling algorithms in your state machine
The ladder logic scheduler design pattern allows you to specify the order in which multiple Simulink® subsystems execute in a single time step.
With the loop scheduler design pattern, you can schedule one Simulink subsystem to execute multiple times in a single time step.
The temporal logic scheduler design pattern allows you to schedule Simulink subsystems to execute at specified times.
You can schedule calls to Simulink and MATLAB® functions by using conditional and time-based logic in Stateflow®.