The temporal logic scheduler design pattern allows you to schedule Simulink® subsystems to execute at specified times. The model sf_temporal_logic_scheduler illustrates this design pattern.
The Temporal Logic Scheduler chart contains the following logic:
The Temporal Logic Scheduler chart contains two states that schedule the execution of the function-call subsystems A1, A2, and A3 at different rates, as determined by the temporal logic operator every (see Operators for Event-Based Temporal Logic).
In the FastScheduler state, the every operator schedules function calls as follows:
Sends A1 every time the function-call output event call wakes up the chart
Sends A2 at half the base rate
Sends A3 at one-quarter the base rate
The SlowScheduler state schedules function calls less frequently — at 8, 16, and 32 times slower than the base rate. The chart switches between fast and slow executions after every 100 invocations of the call event.
To run the sf_temporal_logic_scheduler model, follow these steps:
Open the Scope block.
After the simulation ends, click the Autoscale button in the Scope block.
The scope illustrates the different rates of execution.