Receive data from Analog Devices FMCOMMS board
SDRADIFMCOMMSReceiver System object™ receives
data from a Xilinx® FPGA-based radio, allowing simulation and
development for various software-defined radio applications. The
enables communication with a FPGA board on the same Ethernet subnetwork.
SDRADIFMCOMMSReceiver System object is
a signal sink that receives data from an FPGA board and outputs a
column vector signal of fixed length. The first call to this object
can contain transient values, which results in packets containing
The diagram shows how MATLAB®, the
SDRADIFMCOMMSReceiver System object,
and Xilinx FPGA hardware interface.
Starting in R2016b, instead of using the
The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all specified in the object properties):
|Port||Supported Data Types|
The output port supports the following complex data types only:
When you select a
type, the complex values are scaled to the range of [-1,1]. When
int16, the complex values are the raw
16-bit I and Q samples from the board.
H = comm.SDRADIFMCOMMSReceiver creates
an SDR receiver System object,
H, that receives
data from an FPGA development motherboard with an Analog Devices FMCOMMS
daughterboard installed. The System object enables communication
with an SDR board on the same gigabit Ethernet subnetwork as the host.
H = comm.SDRADIFMCOMMSReceiver( creates
an SDR receiver System object,
H, with the
specified property Name set to the specified Value. You can specify
additional name-value pair arguments in any
order as (Name1,Value1,...,NameN,ValueN).
SDRADIFMCOMMSReceiver System object connects
to a device when you call the step method and stays connected until
you call the release method.
IP address of the radio
Specify the logical network location of the radio as a character
vector. The default is
See also Check Radio Connection.
Source of RF center frequency
Specify the source of the center frequency as
RF center frequency in Hz
Specify the desired center frequency as a double-precision,
nonnegative, finite scalar. This property applies when you set the
The default is
Actual RF center frequency in Hz
Reports the actual center frequency of the daughterboard. Desired
and actual center frequency can differ slightly due to quantization.
The value is
Source of RF intermediate frequency
Specify the source of the intermediate frequency as
Desired intermediate frequency in Hz
The intermediate frequency (IF) tuner allows you to account
for the error in tuning between target center frequency and actual
center frequency and avoid unwanted interference by shifting it out
of the pass band of interest. Specify the desired intermediate frequency
as a double-precision, finite scalar. The default value is
See also Set Intermediate Frequency Tuning.
Actual intermediate frequency in Hz
Reports the actual intermediate frequency. Desired and actual
intermediate frequency can be slightly different due to quantization.
The value is
Source of gain
Specify the source of the overall gain as
Desired overall gain in dB
Specify the desired overall gain as a double-precision, nonnegative
scalar. The default value and the valid range of this property depend
on the RF daughterboard. This property applies when you set the
Actual overall gain in dB
Reports the actual overall gain of the daughterboard. Desired
and actual gain can differ slightly due to quantization. The value
Desired ADC sampling rate in Hz
Specify the desired sampling rate as a double-precision, nonnegative scalar. The default value is 98.304 MHz. The valid range of this property is 39–100 MHz.
Actual ADC sampling rate in Hz
Reports the actual sampling rate of the RF signal. Desired and
actual sampling rate can differ slightly due to quantization. The
Desired decimation factor
Specify the desired decimation factor as a double-precision,
nonnegative scalar. The default is 512. The baseband rate is
See also Apply Decimation Factors.
Actual decimation factor
Reports the actual decimation factor of the daughterboard. Desired
and actual decimation factors can differ slightly due to quantization.
The value is
Output overrun flag
Set this property to true to specify for the step method to output the number of lost samples during host—hardware data transfers.
The default value for
This port is a useful diagnostic tool to determine real time operation of the System object. If your design is not running in real-time, you can increase the decimation factor to approach or achieve real-time performance.
See also Detect Underruns and Overruns.
Data type of output
Specify the complex output data type as
This System object supports the following complex output data types:
Specify the frame length of the output signal that the object generates as a positive, scalar integer. Using values less than 366 can yield very poor performance. The default value is 3660.
See also Set Frame Length.
Ensure a set of frames without overrun or underrun
When set to true, this property produces a set of contiguous
frames without an overrun or underrun to the radio. This setting
can help simulate models that cannot run in real time. When you enable
this property, specify the desired amount of contiguous data using
See also Burst-Mode Buffering
Number of frames in contiguous burst
This property is valid when
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the algorithm generated and programmed during the SDR workflow. This bypass can help with debugging system bringup. The default value is false, or not enabled.
Bypass the DC bias removal filter
When true, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. The default is false, which means to include the automatic DC blocking filter.
You can set the desired values in the receiver System object for the following radio properties. However, due to quantization or range issues, the actual values can differ from your desired values. The actual values are stored in the properties that begin with Actual (see table).
|Parameter to Set||Actual Value|
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board information|
|isLocked||Locked status (logical)|
|release||Allow property value and input characteristics changes|
|step||Receive data from SDR board|
|synchronize||Configure SDR board|
Configure an SDR board at the default IP address to receive at 2.5 GHz with an ADC rate of 100 MHz and a baseband rate of 1 MHz. Save the data using a signal logger System object.
hSDR = comm.SDRADIFMCOMMSReceiver( ... 'CenterFrequency', 2.5e9, ... 'ADCRate', 100e6, ... 'DecimationFactor', 100); hLogger = dsp.SignalLogger; for counter = 1:20 [data, dataLength] = step(hSDR); if (dataLength) step(hLogger, data); end end