Transmit data to Analog Devices FMCOMMS board
Note: The Communications System Toolbox™ Support Package for Xilinx® FPGA-Based Radio will be removed in a future release.
SDRADIFMCOMMSTransmitter System object™ transmits
data to a Xilinx FPGA-based radio, allowing simulation and development
for various software-defined radio applications. The
enables communication with a FPGA board on the same Ethernet subnetwork.
SDRADIFMCOMMSTransmitter System object is
a signal source that transmits data to an FPGA board.
The diagram shows how MATLAB®, the
SDRADIFMCOMMSReceiver System object,
and Xilinx FPGA hardware interface.
Starting in R2016b, instead of using the
The following diagram illustrates the data path for radio signal transmission (when the interpolation filter and IF tuner are in use):
|Port||Supported Data Types|
The input port supports the following complex and real data types:
All input must be frame based.
When you select a
type, the complex values are in the range of [-1,1] and converted
int16. When you select
the complex values are 16-bit I and Q samples that are then sent to
an SDR transmitter System object,
transmits data to an FPGA development motherboard with an Analog Devices
FMCOMMS daughterboard installed. The System object enables communication
with an SDR board on the same gigabit Ethernet subnetwork as the host.
an SDR transmitter object,
H, with the specified
Name set to the specified
You can specify additional name-value pair arguments in any
order as (Name1,Value1,...,NameN,ValueN).
SDRADIFMCOMMSTransmitter System object connects
to a device when you call the
step method, and stays
connected until you call the
IP address of the radio
Specify the logical network location of the radio as a character
vector. The default is
See also Check Radio Connection.
Source of RF center frequency
Specify the source of the center frequency as
RF center frequency in Hz
Specify the desired center frequency as a double-precision,
nonnegative, finite scalar. This property applies when you set
The default is
Actual RF center frequency in Hz
Reports the actual center frequency of the daughterboard. Desired
and actual center frequency can differ slightly due to quantization.
The value is
Source of RF intermediate frequency
Specify the source of the intermediate frequency as
Desired intermediate frequency in Hz.
The intermediate frequency (IF) tuner allows you to account
for the error in tuning between target center frequency and actual
center frequency and avoid unwanted interference by shifting it out
of the pass band of interest. Specify the desired intermediate frequency
as a double-precision, finite scalar. The default value is
See also Set Intermediate Frequency Tuning.
Actual intermediate frequency in Hz
Reports the actual intermediate frequency. Desired and actual
intermediate frequency can be slightly different due to quantization.
The value is
Desired DAC sampling rate in Hz
Specify the desired codec rate as a double-precision nonnegative
scalar. The default is 98 MHz. The valid range of this property is
39–100 MHz. This property applies when you set
Actual DAC sampling rate in Hz
Reports the actual sampling rate of the RF signal. Desired and
actual sampling rate can differ slightly due to quantization. The
Desired interpolation factor
Specify the desired interpolation factor as a double-precision,
nonnegative scalar. The default is 512. The baseband rate is
See also Apply Interpolation Factors.
Actual interpolation factor
Reports the actual interpolation factor of the daughterboard.
Desired and actual interpolation factor can differ slightly due to
quantization. The value is
Output flag to indicate dropped samples
Set this property to true so that the step method outputs the number of lost samples during host-hardware data transfers.
The default value for
This port is useful for determining real-time operation of the System object. If your design is not running in real time, increase the decimation factor to approach or achieve real-time performance.
See also Detect Underruns and Overruns.
Ensure a set of frames without overrun or underrun
When set to true, this property produces a set of contiguous
frames without an overrun or underrun to the radio. This setting
can help simulate models that cannot run in real time. When you enable
this property, specify the desired amount of contiguous data using
See also Burst-Mode Buffering
Number of frames in contiguous burst
This property is valid when
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the
algorithm generated and programmed during the SDR workflow. This bypass
can help with debugging system bringup. The default value is
When you set property values for center frequency, intermediate frequency, DAC, and interpolation, the System object initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware makes a best effort to set the requested value, and reports the actual value in the property that begins with Actual (see table).
|Parameter to Set||Actual Value|
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board information|
|step||Transmit data to SDR board|
|synchronize||Configure SDR board|
|Common to All System Objects|
Create System object with same property values
Expected number of inputs to a System object
Expected number of outputs of a System object
Check locked states of a System object (logical)
Allow System object property value changes
Configure an SDR board with an IP address of 192.168.2.2 to transmit at 2.4 GHz with a codec rate of 100 MHz and a baseband rate of 1 MHz. Use a DPSK modulator as the data source.
hSDR = comm.SDRADIFMCOMMSTransmitter( ... 'IPAddress', '192.168.2.2', ... 'CenterFrequency', 2.4e9, ... 'DACRate', 100e6, ... 'InterpolationFactor', 100); hMod = comm.DPSKModulator('BitInput',true); for counter = 1:20 data = randi([0 1], 30, 1); modSignal = step(hMod, data); step(hSDR, modSignal); end