Receive data from Epiq Solution's Bitshark RF board
Note: The Communications System Toolbox™ Support Package for Xilinx® FPGA-Based Radio will be removed in a future release.
SDREpiqBitsharkReceiver System object™ receives
data from a Xilinx FPGA-based radio, allowing simulation and
development for various software-defined radio applications. The
enables communication with a FPGA board on the same Ethernet subnetwork.
SDREpiqBitsharkReceiver System object is
a signal sink that receives data from an FPGA board and outputs a
column vector signal of fixed length. The first call to this object
may contain transient values which result in packets containing undefined
The following diagram illustrates how MATLAB®, the
SDREpiqBitsharkReceiver System object,
and Xilinx FPGA hardware interface.
Starting in R2016b, instead of using the
The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all specified in the object properties):
|Port||Supported Data Types|
The output port supports these complex data types only:
When you select a
type, the complex values are scaled to the range of [-1,1]. When
int16, the complex values are the raw
16-bit I and Q samples from the board.
H = comm.SDREpiqBitsharkReceiver creates
an SDR receiver System object,
H, that receives
data from an FPGA development motherboard with an Epiq Solution's Bitshark™ FMC-1Rx
daughterboard installed. The System object enables communication
with an SDR board on the same gigabit Ethernet subnetwork as the host.
H = comm.SDREpiqBitsharkReceiver( creates
an SDR receiver System object,
H, with the
specified property Name set to the specified Value. You can specify
additional name-value pair arguments in any order as (Name1,Value1,...,NameN,ValueN).
SDREpiqBitsharkReceiver System object connects
to a device when you call the step method, and will stay connected
until you call the release method.
IP address of the SDR device
Specify the logical network location of the SDR device as a character vector. The default is 192.168.0.2 for Epiq radios.
See also Check Radio Connection.
Source of the center frequency
Specify the source of the center frequency as one of
Desired center frequency in Hz
Specify the desired center frequency as a double-precision,
nonnegative, finite scalar. This property applies when you set the
The default is
Actual center frequency in Hz
Report the actual center frequency of the daughterboard. Desired and actual center frequency can differ slightly due to quantization. This property is read-only.
Source of RF intermediate frequency
Specify the source of the intermediate frequency as
Desired intermediate frequency in Hz
The intermediate frequency (IF) tuner allows you to account
for the error in tuning between target center frequency and actual
center frequency and avoid unwanted interference by shifting it out
of the pass band of interest. Specify the desired intermediate frequency
as a double-precision, finite scalar. The default value is
See also Set Intermediate Frequency Tuning.
Actual intermediate frequency in Hz
Reports the actual intermediate frequency. Desired and actual
intermediate frequency can be slightly different due to quantization.
The value is
Source of bandwidth for IF filter
Desired IF bandwidth in Hz
Actual IF bandwidth in Hz
Source of the gain
Specify the source of the gain as one of
Desired RF front-end gain in dB
Actual RF front-end gain in dB
Report the actual gain of the daughterboard. Desired and actual gain can differ slightly due to quantization. This property is read-only.
Desired ADC sample rate. The default value is 100MHz. The valid range for this board is 5–105MHz.
Actual ADC sample rate in samples per second
Desired decimation factor
Specify the desired decimation factor as a double precision
nonnegative scalar. The default is 512. The baseband rate is
See also Apply Decimation Factors.
Actual decimation factor
Reports the actual decimation factor of the daughterboard. Desired
and actual decimation factor can differ slightly due to quantization.
The value is
Output flag to indicate dropped samples
Set this property to
This port is a useful diagnostic tool to determine real time operation of the System object. If your model is not running in real time, you can increase the decimation factor to approach or achieve real-time performance.
See also Detect Underruns and Overruns.
Data type of output
Specify the data type of the output signal as
When you set
Specify the frame length of the output signal that the object
generates as a positive, scalar integer. The default value is
See also Set Frame Length.
Ensure a set of frames without overrun
When set to true, this property produces a set of contiguous
frames without an overrun or underrun to the radio. This setting
can help simulate models that cannot run in real time. When enabled,
specify the desired amount of contiguous data using the
See also Burst-Mode Buffering
Number of frames in contiguous burst
This property is valid when
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the
algorithm generated and programmed during the SDR workflow. This bypass
can help with debugging system bringup. The default value is
Bypass the DC bias removal filter
When true, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. The default is false, which means to include the automatic DC blocking filter.
You can set the desired values in the receiver System object for the following radio properties. However, due to quantization or range issues, the actual values can differ from your desired values. The actual values are stored in the properties that begin with Actual (see table).
|Parameter to Set||Actual Value|
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board information|
|step||Receive data from SDR board|
|synchronize||Configure SDR board|
|Common to All System Objects|
Create System object with same property values
Expected number of inputs to a System object
Expected number of outputs of a System object
Check locked states of a System object (logical)
Allow System object property value changes
Configure an SDR board with an IP address of 192.168.0.2 to receive at 2.5 GHz with a codec rate of 100MHz and a baseband rate of 1MHz. Save the data using a signal logger System object.
hSDR = comm.SDREpiqBitsharkReceiver( ... 'IPAddress', '192.168.0.2', ... 'CenterFrequency', 2.5e9, ... 'ADCRate', 100e6, ... 'DecimationFactor', 100); hLogger = dsp.SignalSink; for counter = 1:20 [data, dataLength] = step(hSDR); if (dataLength) step(hLogger, data); end end