Epiq Bitshark Receiver

Receive data from Epiq Solution's Bitshark board

Library

Communications System Toolbox Support Package for Xilinx(R) FPGA-Based Radio

Description

The Epiq Bitshark Receiver block supports communication between Simulink® and a Xilinx® FPGA-based radio device, allowing simulation and development for various software-defined radio applications. The Epiq Bitshark Receiver block enables communication with a Xilinx FPGA board on the same Ethernet subnetwork.

The Epiq Bitshark Receiver block is a signal sink that receives data from a Xilinx FPGA board and outputs a column vector signal of fixed length. The first call to this block may contain transient values which result in packets containing undefined data.

The following block diagram illustrates the interaction between Simulink, the Epiq Bitshark Receiver block, and the Xilinx FPGA device.

When this block is called, it is possible that the host may not have received any data from the Xilinx FPGA hardware. The data length port, DataLength, indicates when valid data is present. When the data length port contains a zero value, there is no data. You can use the data length with an enabled subsystem to qualify the execution of part of the model.

If your computer is not connected to any Xilinx FPGA hardware, you can still use this block to develop a model that propagates sample time and data type information. To propagate this information, select Edit > Update diagram; alternatively, you can press Ctrl + D.

To open the SDR Block library, enter the following at the MATLAB® prompt:

>>sdrflib

Data Path

The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all in use in the block):

Supported Data Types

PortSupported Data Types

Data

The output port supports these complex data types only:

  • Double-precision floating point

  • Single-precision floating point

  • 16-bit signed integers

When you select a double or single data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16-bit I and Q samples from the board.

Dialog Box and Parameters

Radio IP address:

Specify the logical network location of the radio as a string. The default IP address is 192.168.0.2 for Epiq Solution radios.

See also Check Radio Connection.

Synchronize

Configure the SDR board and read back the actual hardware values.

Center frequency

Center frequency in Hz

Specify the desired center frequency as a double-precision, nonnegative, finite scalar. The default is 2.4GHz. The valid range of values for this parameter is 300MHz to 4GHz.

Intermediate frequency (Hz)

The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting it out of the pass band of interest. Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is to , where is the analog-digital converter (ADC) rate.

See also Set Intermediate Frequency Tuning.

IF bandwidth

Desired IF bandwidth in Hz.

Gain

Desired RF front-end gain in dB.

ADC sampling rate

Desired ADC sampling rate. The default is 100MHz. The valid range for this board is 5–105MHz.

Decimation factor

Desired decimation factor as a double precision nonnegative scalar. The default is 512. The baseband rate is ADC sampling rate / Decimation factor.

See also Apply Decimation Factors.

Enable lost samples output port

Enable lost samples port

Select this option so that the block outputs a value to indicate if one or more packets is dropped during host reception of FPGA hardware data.

  • Zero indicates no data loss

  • A positive number indicates that overruns or underruns occurred

This port is a useful diagnostic tool to determine real time operation of the receiver block. If your model is not running in real time, you can increase the decimation factor to approach or achieve real-time performance.

See also Detect Underruns and Overruns.

Output data type

Select the data type of the output signal. The default is int16, with a range of [-32768, 32767]. This block supports the following complex output data types:

  • Double-precision floating point

  • Single-precision floating point

  • 16-bit signed integers

When you set Output data type to either Double-precision floating point or Single-precision floating point, the range is [-1, 1].

Sample time

Specifies the sample time for a single radio sample. For the Simulink sample time to correspond to real time, use the following formula: Sample time = 1/(ADC sampling rate/Decimation factor). The default setting for this parameter is 1.

See also Set Sample Times.

Frame length

Specify the frame length of the output signal that the block generates as a positive, scalar integer. Using values less than 366 is not recommended as it may yield very poor performance. The default value is 3660.

See also Set Frame Length.

Enable burst mode

Ensure a set of frames without overruns.

When selected, this option produces a set of contiguous frames without an overrun frame to the radio. This setting can help simulate models that cannot run in real time. When enabled, specify the desired amount of contiguous data using the Number of frames in burst option. The default value is not selected.

See also Burst-Mode Buffering

Number of frames in burst

Number of frames in contiguous burst

This parameter is valid and visible only when the Enable burst mode parameter is selected. The default number of frames in a burst is 20.

Bypass DC blocking filter

Bypass the DC bias removal filter. When you select this parameter, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. By default, this option is not selected, which means to include the automatic DC blocking filter.

Bypass user logic

When you select this option, the FPGA data path bypasses the custom design under test (DUT) logic that is generated and programmed during the SDR Targeting workflow. This bypass helps with debugging system bringup. By default, this option is selected.

Info

Communicate with the attached radio to obtain basic hardware information. The information is displayed in the Hardware Information pane.

Desired vs. Actual Device Block Parameter Values

When you set block values for center frequency, intermediate frequency, IF bandwitdth, gain, ADC and decimation, the block initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware will make a best effort to set the requested value, and will report the actual value in the Device value column of the block mask.

Related Links

Was this topic helpful?