sdrload

Load FPGA and firmware images onto radio

Syntax

  • sdrload('Device',dev,'RFBoard',rfboard) example
  • sdrload(___,Name,Value) example

Description

example

sdrload('Device',dev,'RFBoard',rfboard) loads FPGA and firmware images onto the radio specified by dev and rfboard.

example

sdrload(___,Name,Value) uses additional options specified by one or more Name,Value pair arguments.

Input Arguments

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dev — Device nameXilinx ML605 | Xilinx SP605

Development board that has the radio that you want to load FPGA and firmware images onto, specified as 'Xilinx ML605'.

rfboard — Name of RF boardADI FMCOMMS1 RevB | Epiq Bitshark RevB | Epiq Bitshark RevC

Name of RF board you want to load images onto, specified as one of these values:

  • ADI FMCOMMS1 RevB

  • Epiq Bitshark RevB

  • Epiq Bitshark RevC

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: 'FPGAImage','/mywork/QPSKReceiver.bit'

'FPGAImage' — Name of FPGA programming filefixed bitstream file (default) | string

Name of FPGA programming file, specified as the comma-separated pair consisting of 'FPGAImage' and the filename. Use this option when you are loading a custom programming file generated using the FPGA targeting workflow. The default is the fixed bitstream file that ships with the product for the specified Device and RFBoard.

'Cable' — Logical name assigned by iMPACT for JTAG cableauto (default) | string

Logical name assigned by iMPACT for JTAG cable, specified as the comma-separated pair consistent of 'Cable' and a string. Use this option when there is more than one development board connected to the host via JTAG at the same time. iMPACT enumerates the host USB connections as usb21, usb22, and so on. See Xilinx® documentation for more information. The default value is auto.

Examples

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Load Fixed Bitstream

sdrload('Device','Xilinx ML605', 'RFBoard','Epiq Bitshark RevC'); 

This command loads a custom FPGA image created using the SDR workflow in HDL Workflow Advisor for the ADI FMCOMMS1 RevB RF board and the Xilinx ML605 development board.

Load Custom Bitstream

 sdrload('Device','Xilinx ML605','RFBoard','ADI FMCOMMS1 RevB', ...
                'FPGAImage','/mywork/QPSKReceiver.bit')

This command loads a custom FPGA image created using the SDR workflow in HDL Workflow Advisor for the ADI FMCOMMS1 RevB RF board and the Xilinx ML605 development board.

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