This example shows you how to use FPGA Data Capture with existing HDL code to read FPGA internal signals. We start with an existing FPGA design that implements Xilinx XADC IP to read the on-chip temperature sensor data. The XADC IP exposes a dynamic reconfiguration port (DRP) interface for read and write internal registers. This FPGA design contains some simple logic that reads out the temperature sensor register from XADC IP. To obtain the temperature reading for further analysis, we use FPGA Data Capture feature to read the raw sensor data into MATLAB workspace. Then MATLAB converts the raw temperature data into meaningful Celsius number.
HDL Verifier Support Package for Xilinx FPGA Boards
Xilinx® Vivado® Design Suite
ZedBoard or Xilinx Virtex-7 VC707 development board
1. Make sure that the power switch remains OFF.
2. Connect the AC power cord to the power plug, and plug the power supply adapter cable into the FPGA development board.
3. Connect the JTAG download cable between the FPGA development board and the host computer.
4. Turn on the power switch on the FPGA board.
Set up a working folder and provide MATLAB with access to your FPGA design software.
1. Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.
2. Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:
3. To copy the example FPGA design files into your working directory, enter this MATLAB command:
4. Set up Xilinx Vivado Design Suite. Here, we assume that the Xilinx Vivado executable is located in C:\Xilinx\Vivado\2015.4\bin\vivado.bat. If the location of your executable is different, use your path instead.
At the MATLAB command prompt, enter:
This command launches a graphical user interface (GUI). This example monitors two signals from the existing HDL code for the temperature sensor system. The signals are a 16-bit "temperature", and 8-bit "counter". The "temperature" signal is the reading of register 0x00 from XADC, which stores the converted raw temperature sensor. It has 16bits, but only the 12-bit most significant bits (MSB) are the raw temperature senor reading. The last signal "counter" is an 8-bit free-running counter. To configure the data capture components to operate on these two signals, make the following changes:
1. Add one row to the Signals table by clicking the "Add" button once.
2. Name the first signal to "temperature", and the second signal to "counter".
3. Change the bit widths of the two signals to 16, and 8, respectively.
4. Set the FPGA vendor to Xilinx.
5. Ensure the selected language is Verilog.
6. Change the Sample depth to 1024. This is the number of samples of each signal that the data capture tool returns to MATLAB each time a trigger is detected.
The GUI now looks like this:
Finally, click the "Generate" button to generate FPGA Data Capture component. You should see a report that confirms the generation was successful.
You must include the generated HDL IP core into the example FPGA design. You can copy the module instance code from the generated report. In this example, we are going to connect the generated HDL IP with the temperature sensor output from XADC IP, and an 8-bit free-running counter.
If you are using ZedBoard, open the top.v file provided with this example. If you are using VC707, open the top_vc707.v file. Add the following code immediately above the last line (endmodule) of that file.
datacapture u0 ( .clk(clk), .clk_enable(1'b1), .temperature(do_out), .counter(counter[7:0]));
We also placed above code in top.v/top_vc707.v file but commented it out. You can also uncomment that piece of code instead of adding it.
Save the file you modified, compile the modified FPGA design, and create an FPGA programming file.
If you are using ZedBoard, execute the following command
system('vivado -mode batch -source data_capture_xadc_zedboard.tcl &')
If you are using VC707, execute the following command
system('vivado -mode batch -source data_capture_xadc_vc707.tcl &')
The tcl scripts included in this example perform these steps:
1. Create a new Vivado project.
2. Add example HDL files and the generated FPGA Data Capture HDL files to the project.
3. Compile the design.
4. Program the FPGA.
Wait until the Vivado process successfully finishes before going to the next step. This process takes approximately 5 to 10 minutes.
First, go into the directory where the FPGA Data Capture component is generated.
Launch the FPGA Data Capture App. This app is customized for your data capture signals.
Click the green "Capture Data" button to start data capture. This requests one buffer of captured data from the FPGA. The default is to capture immediately, without waiting for a trigger condition.
The captured data is saved into a struct, dataCaptureOut, in the MATLAB workspace. If you have DSP System Toolbox, the captured data is also displayed as signal waveforms in the Logic Analyzer.
The captured temperate sensor data is in raw format. The sensor data sheet gives the formula for converting it to Celsius units. Calculate and report the average temperature over all the samples returned.
CelsiusTemp = (double(dataCaptureOut.temperature))/(2^4)*503.975/4096 - 273.15; sprintf('The FPGA Temperature is %fC\n',mean(CelsiusTemp))
To capture data from the FPGA around a particular event, you can configure trigger conditions in the FPGA Data Capture App. For example, capture the temperature data only after a counter reaches a certain value.
Select "counter" from the trigger signal dropdown, and click "+" button to enable this trigger signal. Then set the corresponding trigger condition to 10. The trigger mode would automatically change to "On trigger". This tells the FPGA to wait for the trigger condition before capturing and returning data. The GUI now looks like this:
Click Capture Data again. This time the data capture IP returns 1024 samples, captured when it detects the counter equals 10.