Documentation

HDL Verifier Support Package for Xilinx FPGA Boards

Use FPGA-in-the-loop (FIL) verification on Xilinx FPGA boards

HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier™ and supported Xilinx hardware. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code. The HDL code can either be manually written or generated from a model subsystem.

Setup and Configuration

Install hardware support, update firmware, configure hardware connection

FPGA-in-the-Loop Simulation

Verification with FPGA hardware

FPGA Data Capture

Capture signal data from live FPGA

MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB

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