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Simulink Design Verifier Data File Test Vectors

Prerequisites

The Simulink Design Verifier Data File test vector can read test cases created by the Simulink® Design Verifier™ software. In order to use this test vector, you need a Simulink Design Verifier data file with test cases.

To use this feature, you first run Simulink Design Verifier with the appropriate configuration. Then you can do one of two things:

  • Generate a SystemTest™ harness for the model from Simulink. When it completes, a new test opens automatically in SystemTest and a Simulink Design Verifier Data File test vector is automatically created. This workflow is described in Create SystemTest Harness from Simulink Design Verifier.

  • If you already have a data file from Simulink Design Verifier, you can create a test vector in SystemTest that uses the test cases in the data file, and configure overrides in a Simulink element. This workflow is described in Create a Simulink Design Verifier Test Vector.

Create SystemTest Harness from Simulink Design Verifier

If you generate a SystemTest test harness from Simulink using Simulink Design Verifier, a new test opens automatically in SystemTest with a Simulink Design Verifier Data File test vector and a Simulink element automatically created for you. The following steps outline this workflow.

  1. From your model, select Analysis > Design Verifier > Options.

  2. In the Configuration Parameters dialog box, select Design Verifier > Results, and then enable the Save test harness as SystemTest TEST-file option.

  3. Click OK.

  4. In Simulink, save the model.

  5. From your model, select Analysis > Design Verifier > Generate Tests to run the model and generate the SystemTest test harness.

    After the model generates test cases, the SystemTest software opens automatically. A Simulink Design Verifier Data File test vector containing the generated test inputs is automatically created. A Simulink element is also created, configured with the model name, override mappings set, and model coverage enabled.

  6. Optionally, in the SystemTest software, you can add other things to the test, such as a plot element. For an example of this, see Create a Simulink Design Verifier Test Vector.

  7. Run the test in the SystemTest software by clicking the Run button.

Create a Simulink Design Verifier Test Vector

If you already have a data file from Simulink Design Verifier, you can create a test vector in the SystemTest software that uses the generated rest cases in the data file, and configure overrides in a Simulink element. The following steps outline this workflow.

  1. In the Test Vectors pane, click the New button.

  2. In the Insert Test Vector dialog box, select Simulink Design Verifier Data File as the test vector type.

  3. Accept the default test vector name, or type a new one in the Name field.

  4. Type the name of the Simulink Design Verifier data file in the Type field, or use the Browse button to locate it. It will be a .mat file.

    Note that you must use a valid MAT-file – a Simulink Design Verifier data file created in version R2008b or later. If you try to use a data file created in an earlier version of the software or a MAT-file that is not generated from Simulink Design Verifier, you will get an error.

  5. When the data file is read in, the test cases appear in the Test Cases Name table. Click any test case to see its test case description below the table.

  6. To see information from the Simulink Design Verifier data file, click the Details tab. This provides analysis information on the data file, and the model Inport blocks associated with the test cases. If the test cases involve any model parameter configurations, they appear in the Parameters section. This section will list any parameters that are used as part of a test case. The information in this tab is not editable.

  7. Click the OK button to finish creating the new test vector. It then appears in the Test Vectors pane in the SystemTest desktop.

    Now that the test vector is created, you can create mappings in a Simulink element.

  8. Create a Simulink element by clicking the Main Test node in the Test Browser, and clicking the New button. Select Test Element > Simulink.

  9. Type the name of the model, or use the Browse button to locate it. This should be the same model that was used to create the Simulink Design Verifier data file.

    If you browsed for the file, when you click OK, the model opens.

  10. In the Override Inport Block Signals with SystemTest Data section of the Simulink element, select the All Inport blocks are mapped using option. You must select this option in order to correctly use the Simulink Design Verifier data file.

  11. From the drop-down list, select the test vector you created earlier in this workflow.

    In the example shown here, the model name is sldvdemo_cruise_control.slx and the vector is TestVector1.

  12. If you have the Simulink Verification and Validation™ software and you want to use the Model Coverage feature in the Simulink element, click the Model Coverage tab.

  13. Select the Enable Model Coverage check box.

  14. Select Override model coverage metric settings.

  15. Select any metrics you want to cover in the Coverage Metrics section.

  16. Optionally, if you want to plot any of the signals, create a plot element.

    Select the Simulink element you already created in the Test Browser, and select New > Test Element > Plot – General.

  17. In the Plot element, click the Add Plot button.

  18. Select Simulink Data.

  19. From the Simulink Data field, expand the test vector that you created to see the individual signals.

  20. Select one of the signals, for example, speed.

  21. Run the test by clicking the Run button on the SystemTest toolbar.

    In this example, after the test runs, a model coverage report and a plot of the speed signal are generated.

Important Usage Notes

The following notes pertain to the integration between the SystemTest software and Simulink Design Verifier using the Simulink Design Verifier Data File test vector:

  • Model Coverage Report — The model coverage report generated by the model harness using Simulink Verification and Validation and that of the SystemTest harness generated by Simulink Design Verifier will be identical.

  • Data Format — The format of the data from a Simulink Design Verifier Data File test vector, if seen in a MATLAB element or in saved test results for example, is a subset of the Simulink Design Verifier data format.

    It is a MATLAB structure with one field, TestCases. Then the TestCases field contains two fields, dataValues and paramValues. TestCases is a 1x1 structure. The following figure shows the data format for a Simulink Design Verifier Data File test vector called TestVector1:

  • Data file Version — To use the Simulink Design Verifier Data File test vector, you must use a Simulink Design Verifier data file created in version R2008b or later. If you try to use a data file created in an earlier version of the software or a MAT-file that is not generated from Simulink Design Verifier, you will get an error.

  • Evaluating the Test Vector — If you make changes in the underlying Simulink Design Verifier test cases, you can click the Evaluate button in the Test Vectors pane any time to see the changes reflected in the SystemTest user interface. However this is not necessary to pick up the changes for running the test. When you run a test containing a Simulink Design Verifier Data File test vector, the SystemTest software automatically queries the data file for the latest information in the test cases.

  • Changing the Underlying Model — If you make changes in the underlying Simulink model, such as changes to Inport blocks, you should return to Simulink Design Verifier and regenerate the test cases and the test harness. Then return to SystemTest test harness to continue working with your test.

  • Model End Time — In the use case where you automatically generate the SystemTest test harness from Simulink Design Verifier, the end time used will be that of the test cases per iteration. However, in the use case where you create the test vector in SystemTest using a Simulink Design Verifier data file that you already have, the underlying model's end time will be used per iteration.

  • Bus Support — The Simulink Design Verifier Data File test vector supports the use of busses in Inport blocks. Bus support is only available in SystemTest through this feature.

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