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| R2012a Documentation → Embedded Coder | |
Learn more about Embedded Coder |
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| Contents | Index |
Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C2000/ C2802x
Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C2000/ C2803x
Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C2000/ C280x
Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C2000/ C28x3x
Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C2000/ C2834x
Configures the Event Manager of the C280x/C2802x/C2803x/C28x3x DSP to generate ePWM waveforms. These DSPs contain multiple ePWM modules. Each module has two outputs, ePWMA and ePWMB. You can use the ePWM block to configure up to six ePWM modules.
When you enable the High-Resolution Pulse Width Modulator (HRPWM), the ePWM block uses the Scale Factor Optimizing Software Version 5 library (SFO_TI_Build_V5.lib). SFO_TI_Build_V5.lib can "dynamically determine the number of MEP steps per SYSCLKOUT period." For more information, consult TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number SPRU924, available at the Texas Instruments Web site.
Enable all 16 High-Resolution PWM modules (HRPWM) on the C28044 digital signal controller when the PWM resolution is too low.
For example, the Spectrum Digital eZdsp™ F28044 board has a system clock of 100 MHz (200-kHz switching). At these frequencies, conventional PWM resolution is too low—approximately 9 bits or 10 bits. By comparison, the HRPWM resolution for the same board is 14.8 bits.
All the C280x/C2802x/C2803x/C28x3x/c2834x ePWM blocks in your model become HRPWM blocks, Thus, when you enable this parameter:
Use the HRPWM parameters under the ePWMA tab to make additional configuration changes.
Most of the configuration parameters under the ePWMB tab are unavailable.
Your model can contain up to 16 C280x/C2803x/C28x3x ePWM blocks, provided you configure each one for a separate module. (For example, Module is ePWM1, ePWM2, and so on.)
For processors other than the C28044, deselect (disable) Allow use of 16 HRPWMs (for C28044) instead of 6 PWMs. To enable HRPWM for other processors, first determine how many HRPWM modules are available. Consult the Texas Instruments documentation for your processor, and then use the HRPWM parameters under the ePWMA tab to enable and configure HRPWM.
For additional information about the C28044 and HRPWM, consult the References section.
Specify which target ePWM module to use.
Specify the units of the Timer period or Timer initial period as Clock cycles (the default) or Seconds. When Timer period units is Seconds, the software down-converts the Timer period or Timer initial period, a double for the period register to a uint16. For best performance, select Clock cycles. Doing so reduces calculations and rounding errors.
Configure the source of the timer period value. Selecting Specify via dialog changes the following parameter to Timer period. Selecting Input port changes the following parameter to Timer initial period and creates a timer period input port, T, on the block.
Set the period of the PWM waveform in clock cycles or in seconds, as determined by the Timer period units parameter. When you enable HRMWM, you can enter a high-precision floating point value. The Time-Base Period High Resolution Register (TBPRDHR) stores the high-resolution portion of the timer period value.
The period of the waveform from the time the PWM peripheral starts operation until the ePWM input port, T, receives a new value for the period. Use Timer period units to measure the period in clock cycles or in seconds.
Specify the counting mode in which to operate. This PWM module can operate in three distinct counting modes: Up, Down, and Up-Down. The Down option is not compatible with HRPWM. To avoid an error when you build the model, do not set the Counting mode parameter to Down and select the Enable HRPWM (Period) parameter checkbox.
The following illustration shows the waveforms that correspond to these three modes:
This parameter corresponds to the SYNCOSEL field in the Time-Base Control Register (TBCTL).
Use this parameter to specify the event that generates a Time-base synchronization output signal, EPWMxSYNCO, from the Time-base (TB) submodule.
The available choices are:
EPWMxSYNCI or SWFSYNC — a Synchronization input pulse or Software forced synchronization pulse, respectively. You can use this option to achieve precise synchronization across multiple ePWM modules by daisy chaining multiple Time-base (TB) submodules.
CTR=Zero — Time-base counter equal to zero (TBCTR = 0x0000)
CTR=CMPB — Time-base counter equal to counter-compare B (TBCTR = CMPB)
Disable — Disable the EPWMxSYNCO output (the default)
Create an input port, SYNC, for a Time-base synchronization input signal, EPWMxSYNCI. You can use this option to achieve precise synchronization across multiple ePWM modules by daisy-chaining multiple Time-base (TB) submodules.
This parameter only appears in the C2802x and C2803x ePWM blocks.
Synchronize the ePWM time base to a DCAEVT1 digital compare event. Use this feature to synchronize this PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value. This option is not compatible with HRPWM. Enabling HRPWM disables this option.
This parameter only appears in the C2802x and C2803x ePWM blocks.
Synchronize the ePWM time base to a DCBEVT1 digital compare event. Use this feature to synchronize this PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value. This option is not compatible with HRPWM. Enabling HRPWM disables this option.
Specify the source of a phase offset to apply to the Time-base synchronization input signal, EPWMxSYNCI from the SYNC input port. Selecting Specify via dialog creates the Phase offset value parameter. Selecting Input port creates a phase input port, PHS, on the block. Selecting Disable, the default value, prevents the application of phase offsets to the TB module.
This parameter appears when Counting Mode is Up-Down and Phase offset source is Specify via dialog or Input port. Configure the timer to count up from zero, or down to zero, following synchronization. This parameter corresponds to the PHSDIR field of the Time-base Control Register (TBCTL).
This field appears when you select Specify via dialog in Phase offset source.
Configure the phase offset (delay) between the following events:
The arrival of the Time-base synchronization input signal (EPWMxSYNCI) on the SYNC input port
The moment the Time-base (TB) submodule synchronizes the ePWM module.
This parameter corresponds to the Time-Base Phase Register (TBPHS).
Use the TB clock prescaler divider (CLKDIV) and the High Speed TB clock prescaler divider (HSPCLKDIV) to configure the Time-base clock speed (TBCLK) for the ePWM module. Calculate TBCLK using the following equation:
TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)
For example, the default values of both CLKDIV and HSPCLKDIV are 1, and the default frequency of SYSCLKOUT is 100 MHz, so:
TBCLK = 100 MHz = 100 MHz/(1 * 1)
The choices for the TB clock prescaler divider are: 1, 2, 4, 8, 16, 32, 64, and 128.
The TB clock prescaler divider parameter corresponds to the CLKDIV field of the Time-base Control Register (TBCTL).
Note The frequency of SYSCLKOUT depends on the oscillator frequency and the configuration of PLL-based clock module. Changing the values of the PLL Control Register (PLLCR) affects the timing of all ePWM modules. For more information, consult the "PLL-Based Clock Module" section of the data manual for your specific target (see References). |
See the TB clock prescaler divider topic for an explanation of the role of this value in setting the speed of the Time-base Clock. Choices are to divide by 1, 2, 4, 6, 8, 10, 12, and 14. Selecting Enable HRPWM (Period) forces this option to 1.
This parameter corresponds to the HSPCLKDIV field of the Time-base Control Register (TBCTL).
This parameter only appears in the C2802x and C2803x ePWM blocks.
Swap the ePWMA and ePWMB outputs. This option outputs the ePWMA signals on the ePWMB outputs and the ePWMB signals on the ePWMA outputs.
This parameter only appears in the C2802x and C2803x ePWM blocks.
When the effective resolution for conventionally generated PWM is insufficient, consider using High Resolution PWM (HRPWM). The resolution of PWM is normally dependent upon the PWM frequency and the underlying system clock frequency. To address this limitation, HRPWM uses Micro Edge Positioner (MEP) ™ technology to position edges more finely by dividing each coarse system clock. The accuracy of the subdivision is on the order of 150ps. The following figure shows the relationship between one system clock and edge position in terms of MEP steps:
Enable HRPWM mode and control it via the Extension Register for HRPWM Period (TBPRDHR) register. When you enable this parameter, you can enter an 8–bit floating point value in for the Timer period parameter. This parameter enables the Enable HRPWM (CMP) option, and displays the HRPWM loading mode, HRPWM control mode, and HRPWM edge control mode options. Also configure HRPWM control mode.
Selecting Enable HRPWM (Period) forces TB clock prescaler divider and High Speed TB clock prescaler divider to 1. These settings match the HRPWM time base clock with the SYSCLKOUT frequency.
The Down option in the Counting mode parameter is not compatible with HRPWM. To avoid an error when you build the model, do not set the Counting mode parameter to Down and select the Enable HRPWM (Period) parameter checkbox.
This parameter only appears in the C2802x and C2803x ePWM blocks.
Enable HRPWM mode and control it via the Extension Register for HRPWM Duty (CMPAHR) register. Also configure HRPWM control mode.
Determine when to transfer the value of the CMPAHR shadow to the active register:
CTR=ZERO: Transfer the value when the time base counter equals zero (TBCTR = 0x0000).
CTR=PRD: Transfer the value when the time base counter equals the period (TBCTR = TBPRD).
CTR=Zero or CTR=PRD Transfer the value when either case is true.
This option configures the HRLOAD "Shadow Mode Bit" in the HRPWM Configuration Register (HRCNFG).
Select which register controls the Micro Edge Positioner (MEP) step size. The HRPWM control mode option configures the CTLMODE "Control Mode Bits".
Duty control mode uses the Extension Register for HRPWM Duty (CMPAHR) or the Extension Register for HRPWM Period (TBPRDHR) to control the MEP edge position.
Select Phase control mode to use the Time Base Period High-Resolution Register (TBPRDHR) to control the MEP edge position.
The HRPWM control mode option configures the CTLMODE "Control Mode Bits" in the HRPWM Configuration Register (HRCNFG).
Swap the ePWMA and ePWMB outputs. This parameter sets the SWAPAB field in the HRPWM Configuration Register (HRCNFG).
Enable scale factor optimizing (SFO) software with HRPWM. This software dynamically determines the appropriate scaling factor for the Micro Edge Positioner (MEP) step size. The step size varies depending on operating conditions such as temperature and voltage. The SFO software reduces variability due to these conditions. For more information, see the "Scale Factor Optimizing Software (SFO)" section of the TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number: SPRUGE8.
This parameter only appears in the C2802x and C2803x ePWM blocks.
Apply the scaling factor calculated by the SFO software to the controlling period or duty cycle. (Use the HRPWM control mode to select controlling period or duty cycle.) This parameter sets the AUTOCONV field in the HRPWM Configuration Register (HRCNFG).
Each ePWM module has two outputs, ePWMA and ePWMB. The ePWMA output pane and ePWMB output pane include the same settings, although the default values vary in some cases, as noted.
Enables the ePWMA and/or ePWMB output signals for the ePWM module identified on the General pane. By default, Enable ePWMxA is enabled, and Enable ePWMxB is disabled.
Specify the units used by the compare register: Percentages (the default) or Clock cycles.
Notes
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Specify the source of the pulse width. If you select Specify via dialog (the default), enter a value in the CMPA value or CMPB value field. If you select Input port, set the value using an input port, WA or WB, on the block. If you select Input port also set CMPA initial value or CMPB initial value.
This field appears when you choose Specify via dialog in CMPA source or CMPB source. Enter a value that specifies the pulse width, in the units specified in CMPA units or CMPB units.
This field appears when you set CMPA source or CMPB source to Input port. Enter the initial pulse width of CMPA or CMPB the PWM peripheral uses when it starts operation. Subsequent inputs to the WA or WB ports change the CMPA or CMPB pulse width.
These settings, along with the other remaining settings in the ePWMA output and ePWMB output panes, determine the behavior of the Action Qualifier (AQ) submodule. The AQ module determines which events are converted into various action types, producing the required switched waveforms of the ePWMxA and ePWMxB output signals.
For each of these four fields, the available choices are Do nothing, Clear, Set, and Toggle.
The default values for these fields vary between the ePWMA output and ePWMB output panes.
The following table shows the defaults for each of these panes when you set Counting mode to Up or Up-Down:
| Action when counter =... | ePWMA output pane | ePWMB output pane |
|---|---|---|
| ZERO | Do nothing | Do nothing |
| PRD | Clear | Set |
| CMPA on CAU | Set | Do nothing |
| CMPA on CAD | Do nothing | Do nothing |
| CMPB on CBU | Do nothing | Clear |
| CMPB on CBD | Do nothing | Do nothing |
The following table shows the defaults for each of these panes when you set Counting mode to Down:
| Action when counter =... | ePWMA output pane | ePWMB output pane |
|---|---|---|
| ZERO | Do nothing | Do nothing |
| PRD | Clear | Set |
| CMPA on CAD | Do nothing | Do nothing |
| CMPB on CBD | Do nothing | Do nothing |
For a detailed discussion of the AQ submodule, consult the TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (SPRU791), available on the Texas Instruments Web site.
These four settings determine how the action-qualifier (AQ) submodule handles the S/W force event, an asynchronous event initiated by software (CPU) via control register bits.
Compare value reload condition determines if and when to reload the Action-qualifier S/W Force Register from a shadow register. Choices are Load on CTR=Zero (the default), Load on CTR=PRD, Load on either, and Freeze.
Add continuous S/W force input port creates an input port, SFA, which you can use to control the software force logic. Send one of the following values to SFA as an unsigned integer data type:
0 = Forcing Disable: Do nothing. The default.
1 = Forcing Low: Clear low
2 = Forcing High: Set high
If you did not create the SFA input port, you can use Continuous S/W force logic to select which type of software force logic to apply. The choices are:
Forcing Disable: Do nothing. The default.
Forcing Low: Clear low
Forcing High: Set high
Reload condition for S/W force — Choices are Zero (the default), Period, Either period or zero, and Immediate.
Only the ePWMB pane on the C2802x and C2803x blocks displays this option. Invert the ePWMxA signal and output it on the ePWMxB outputs. This parameter sets the SELOUTB field in the HRPWM Configuration Register (HRCNFG).
This parameter appears at this position in the C280x and C2833x ePWM blocks.
Select to enable High Resolution PWM settings. When the effective resolution for conventionally generated PWM is insufficient, consider High Resolution PWM (HRPWM). The resolution of PWM is normally dependent upon the PWM frequency and the underlying system clock frequency. To address this limitation, HRPWM uses technology to position edges more finely by dividing each coarse system clock. The accuracy of the subdivision is on the order of 150ps. The following figure shows the relationship between one system clock and edge position in terms of MEP steps:
This parameter appears at this position in the C280x and C2833x ePWM blocks.
Determine when to transfer the value of the CMPAHR shadow to the active register:
CTR=ZERO: Transfer the value when the time base counter equals zero (TBCTR = 0x0000).
CTR=PRD: Transfer the value when the time base counter equals the period (TBCTR = TBPRD).
CTR=Zero or CTR=PRD Transfer the value when either case is true.
This parameter appears at this position in the C280x and C2833x ePWM blocks.
Select which register controls the Micro Edge Positioner (MEP) step size. The HRPWM control mode option configures the CTLMODE "Control Mode Bits".
Duty control mode uses the Extension Register for HRPWM Duty (CMPAHR) or the Extension Register for HRPWM Period (TBPRDHR) to control the MEP edge position.
Select Phase control mode to use the Time Base Period High-Resolution Register (TBPRDHR) to control the MEP edge position.
The HRPWM control mode option configures the CTLMODE "Control Mode Bits" in the HRPWM Configuration Register (HRCNFG).
This parameter appears at this position in the C280x and C2833x ePWM blocks.
Swap the ePWMA and ePWMB outputs. This parameter sets the SWAPAB field in the HRPWM Configuration Register (HRCNFG).
Enable scale factor optimizing (SFO) software with HRPWM. This software dynamically determines the appropriate scaling factor for the Micro Edge Positioner (MEP) step size. The step size varies depending on operating conditions such as temperature and voltage. The SFO software reduces variability due to these conditions. For more information, see the "Scale Factor Optimizing Software (SFO)" section of the TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number: SPRUGE8.
The Deadband unit pane lets you specify parameters for the Dead-Band Generator (DB) submodule.
Enables a deadband area of no signal overlap between pairs of ePWM output signals. This check box is cleared by default.
This parameter only appears in the C2802x and C2803x ePWM blocks.
To double the deadband resolution, enable half-cycle clocking. This option clocks the deadband counters at TBCLK*2. When you disable this option, the deadband counters use full-cycle clocking (TBCLK*1).
Configure the deadband polarity as AH (active high, the default), AL (active low), AHC (active high complementary), or ALC (active low complementary).
Specify the source of the control logic. Choose Specify via dialog (the default) to enter explicit values, or Input port to use a value from the input port.
This field appears only when you select Use deadband for ePWMxA in the ePWMA output pane. Enter a value from 0 to 1023 to specify a rising edge delay.
This field appears only when you select Use deadband for ePWMxB in the ePWMB output pane. Enter a value from 0 to 1023 to specify a falling edge delay.
Configure ADC Start of Conversion (SOC) by one or both of the ePWMA and ePWMB outputs.
When you select this option, ePWM starts the Analog-to-Digital Conversion (ADC) for module A. By default, the software clears (disables) this option.
When you select Enable ADC start module A, this field specifies the number of the event that triggers ADC Start of Conversion for Module A (SOCA): First event triggers ADC start of conversion with every event (the default). Second event triggers ADC start of conversion with every second event. Third event triggers ADC start of conversion with every third event.
When you select Enable ADC start module A, this field specifies the counter match condition that triggers an ADC start of conversion event. The choices are:
(For C2802x and C2803x only) When the ePWM asserts a DCAEVT1 or DCBEVT1 digital compare event. Use this feature to synchronize this PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value.
When the ePWM counter reaches zero (the default).
When the ePWM counter reaches the period value.
When the time base counter equals zero (TBCTR = 0x0000) or when the time base counter equals the period (TBCTR = TBPRD).
When the ePWM counter reaches the compare A value on the way up.
When the ePWM counter reaches the compare A value on the way down.
When the ePWM counter reaches the compare B value on the way up.
When the ePWM counter reaches the compare B value on the way down.
When you select this option, ePWM starts the Analog-to-Digital Conversion (ADC) for module B. By default, the software clears (disables) this option.
When you select Enable ADC start module B, this field specifies the number of the event that triggers ADC start of conversion: First event triggers ADC start of conversion with every event (the default), Second event triggers ADC start of conversion with every second event, and Third event triggers ADC start of conversion with every third event.
When you select Enable ADC start module B, this field specifies the counter match condition that triggers an ADC start of conversion event. The choices are the same as for Module A counter match event condition.
Select this option to generate interrupts based on different events defined by Number of event for interrupt to be generated and Interrupt counter match event condition. By default, the software clears (disables) this option.
When you select Enable ePWM interrupt, this field specifies the number of the event that triggers the ePWM interrupt: First event triggers ePWM interrupt with every event (the default), Second event triggers ePWM interrupt with every second event, and Third event triggers ePWM interrupt with every third event.
When you select Enable ePWM interrupt, this field specifies the counter match condition that triggers ePWM interrupt. The choices are the same as for Module A counter match event condition.
The PWM chopper control pane lets you specify parameters for the PWM-Chopper (PC) submodule. The PC submodule uses a high-frequency carrier signal to modulate the PWM waveform generated by the AQ and DB modules.
Select to enable the chopper module. Use of the chopper module is optional, so this check box is cleared by default.
Set the prescaler value that determines the frequency of the chopper clock. The system clock speed is divided by this value to determine the chopper clock frequency. Choose an integer value from 1 to 8.
Choose an integer value from 1 to 16 to set the width of the first pulse. This feature provides a high-energy first pulse for a hard and fast power switch turn on.
The duty cycles of the second and subsequent pulses are also programmable. Choices are 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, and 87.5%.
The Trip Zone unit pane lets you specify parameters for the Trip-zone (TZ) submodule. Each ePWM module receives six TZ signals (TZ1 to TZ6) from the GPIO MUX. These signals indicate external fault or trip conditions. Use the settings in this pane to program the EPWM outputs to respond when faults occur.
Specify the source of the control logic to enable or disable the TZ Interrupts (One shot TZ1-TZ6 and Cyclic TZ1-TZ6). Select Specify via dialog (the default) to enable specific Trip-zone signals in the block dialog. Choose Input port to enable specific Trip-zone signals using a block input port, TZSEL.
If you select Input port, use the following bit operation to determine the value of the 16-bit integer to send to the TZSEL input port:
TZSEL INPUT VALUE = (OSHT6*213 + OSHT5*212 + OSHT4*211 + OSHT3*210 + OSHT2*29 + OSHT1*28 + CBC6*25 + CBC5*24 + CBC4*23 + CBC3*22 + CBC2*21 + CBC1*20)
The software uses the higher 8 bits for the One shot TZ1-TZ6 and the lower 8 bits for Cyclic TZ1-TZ6. You can set up a group of TZ sources (1~6), use a bit operation to combine them into an integer, and then feed the integer to TZSEL.
For example, to enable One Shot TZ6 (OSHT6) and One Shot TZ5 (OSHT5) as trip zone sources, set OSHT6 and OSHT5 to "1" and leave the remaining values as "0".
TZSEL INPUT VALUE = (1*213 + 1*212 + 0*211 …)
TZSEL INPUT VALUE = (8192 + 4096 + 0 …)
TZSEL INPUT VALUE = 12288
When the block receives this value, it applies it to the TZSEL register as a binary value: 11000000000000.
For more information, see the "Trip-Zone Submodule Control and Status Registers" section of the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRU791 on www.ti.com
Select any of these check boxes to enable the corresponding Trip-zone signal in One-Shot Mode. In this mode, when the trip event is active, the software performs the corresponding action on the EPWMxA/B output immediately and latches the condition. You can unlatch the condition using software control.
Select any of these check boxes to enable the corresponding Trip-zone signal in Cycle-by-Cycle Mode. In this mode, when the trip event is active, the software performs the corresponding action on the EPWMxA/B output immediately and latches the condition. In Cycle-by-Cycle Mode, the software automatically clears condition when the PWM Counter reaches zero. Therefore, in Cycle-by-Cycle Mode, every PWM cycle resets or clears the trip event.
Generate an interrupt when the one shot (OST) triggering event occurs.
Generate an interrupt when the cyclic or cycle-by-cycle (CBC) triggering event occurs.
Upon a fault condition, the software overrides and forces the ePWMxA and/or ePWMxB outputs to one of the following states: No action (the default), High, Low, or Hi-Z (High Impedance).
Use the Digital Compare pane to configure the Digital Compare (DC) submodule.
Each digital compare (DC) submodule receives three TZ signals (TZ1 to TZ3) from the GPIO MUX, and three COMP signals from the COMP. These signals indicate fault or trip conditions that are external to the PWM submodule. Use the settings in this pane to output specific DC events in response to those external signals. These DC events feed directly into the Time-base, Trip-zone, and Event-trigger submodules.
For more information, see the "Digital Compare (DC) Submodule" section of the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRUGE9.
If the TZ or COMP event you select occurs, assert a high signal. Qualify this signal using the Generate DCAEVT#, Generate DCBEVT# options.
If the TZ or COMP event you select occurs, assert a low signal. Qualify this signal using the Generate DCAEVT#, Generate DCBEVT# options.
Qualify the signals that generate DC events, such as DCAEVT# or DCBEVT#. Select the states of DCAH, DCBH, DCAL, and DCBL that generate the event. To disable this feature, choose the Event disabled option.
This parameter controls two separate aspects of triggering DC events:
Triggering filtered or unfiltered DC event. (Configures DCACTL[EVT1SRCSEL] or DCACTL[EVT2SRCSEL].)
Trigger the DC event synchronously or asynchronously. (Configures DCACTL[EVT1FRCSYNCSEL] or DCACTL[EVT2FRCSYNCSEL].)
Filtering
Options that begin with DCAEVT# or DCAEVT# do not apply filtering to DC events. Qualified signals trigger DC events.
Options that begin with DCEVTFILT apply filtering to DC events. Qualified signals pass through filtering circuits before triggering DC events. This filtering is not configurable in the ePWM block. For more information, refer to the "Event Filtering" section of the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRUGE9.
Synchronizing
Options that end with async trigger DC events asynchronously. When the qualified or filtered signals exist, the DC submodule triggers the DC event immediately.
Options that end with sync trigger DC events synchronously. Once the qualified or filtered signals exist, the DC submodule triggers the DC event in sync with the TBCLK signal.
For more information, consult the following references, available at the Texas Instruments Web site:
TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, literature number SPRU791
TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator Reference Guide, literature number SPRU924E
TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, literature number SPRUGE9
TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, literature number SPRUGE8
Using the ePWM Module for 0% - 100% Duty Cycle Control Application Report, literature number SPRU791
Configuring Source of Multiple ePWM Trip-Zone Events, literature number SPRAAR4
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs Data Manual, literature number SPRS230
TMS320F28044 Digital Signal Processor Data Manual, literature number SPRS357
TMS320F28335/28334/28332 TMS320F28235/28234/28232 Digital Signal Controllers (DSCs) Data Manual, literature number SPRS439
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