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Embedded Coder/ Embedded Targets/ Processors/ Texas Instruments C6000/ Optimization/ C64x DSP Library
The C64x Radix-2 IFFT block computes the radix-2 inverse FFT of each channel of a complex input signal. This block uses a decimation-in-frequency forward FFT algorithm with butterfly weights modified to compute an inverse FFT. The input length of each channel must be both a power of two and in the range 16 to 32,768, inclusive. The input must also be in natural (linear) order. The output of this block is a complex signal in bit-reversed order. Inputs and outputs are signed 16-bit fixed-point data types.
The radix2 routine used by this block employs a radix-2 FFT of length L=2^k. So that the gain of the block matches that of the theoretical IFFT, the Radix-2 IFFT block offsets the location of the binary point of the output data type by k bits to the left relative to the location of the binary point of the input data type. That is, the number of fractional bits of the output data type equals the number of fractional bits of the input data type plus k.
OutputFractionalBits = InputFractionalBits+(k)
You can use the C64x Bit Reverse block to reorder the output of the Radix-2 IFFT block to natural order.
The Radix-2 IFFT block supports both continuous and discrete sample times. This block supports little-endian code generation.
In simulation, the Radix-2 IFFT block is equivalent to the TMS320C64x DSP Library assembly code function DSP_radix2. During code generation, this block calls the DSP_radix2 routine to produce optimized code.
C64x Bit Reverse, C64x FFT, C64x Radix-2 FFT
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