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Simulink Coder/ Desktop Targets
Embedded Coder/ Embedded Targets
Use the Target Preferences block to configure a model to for a specific IDE/tool chain, board, and processor. Your MathWorks software depends on this information to properly simulate the model and generate code for your environment.
The appearance and contents of the Target Preferences block varies widely, depending on the options you have selected. The following sections describe all of the user interface elements in the Target Preferences block, even though the Target Preferences block cannot simultaneously display all of the user interface elements.
For more information, see the Target Preferences topic in the User's Guide.
Note The following actions update the appropriate model Configuration Parameters with new values:
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Note If you are using a Windows host, use mapped network drives instead of UNC paths to specify directory locations. Using UNC paths with compilers that do not support them causes build errors. |
Note The figures in this documentation include references to various third-party vendors and products. These images aid with recognition of specific user interface elements. Do not infer a preference or endorsement for any vendor or product over another. |
This reference page section contains the following subsections:
Use the IDE/Tool Chain parameter to select the Integrated Development Environment (IDE) or software build tool chain with which you are working. Selecting any option automatically applies that selection to the Target Preferences block and updates the panes and options the block displays.
Target Preferences block dialog box provides tabbed access to the following panes:
Board Pane — Select the target board, processor, clock speed, and, in some cases, RTOS. In addition, Add new on this pane opens the Add Processor dialog box.
Memory Pane — Set the memory allocation and layout on the processor (memory mapping).
Section Pane — Determine the arrangement and location of the sections on the processor and compiler information.
DSP/BIOS Pane — For Texas Instruments CCS IDE and C6000 processors: Specify how to configure tasking features of DSP/BIOS™.
Peripherals Pane — For Texas Instruments CCS IDE and C2000 processors: Specify how to configure the peripherals provided by C2xxx processors, such as the SPI_A, SPI_B, GPIO, or eCAP peripherals.
Linux Pane — For the Eclipse IDE: Specify the scheduling mode and base rate task priority of the software to run on a Linux target.
VxWorks Pane — For the Wind River Diab/GCC (makefile generation only): Specify the scheduling mode of the software to run on a VxWorks target.
The following options appear on the Board pane, which has separate panels for Board Properties, Board Support, and IDE Support labels.
Select your target board from the list of options. Selecting a specific board sets the appropriate value for the Processor parameter. If you select a custom board, also set the Processor parameter to an appropriate value.
The Board and Processor settings apply default values to many of the remaining Target Preferences parameters, such as those under the Memory and Section tabs.
If the coder product supports an operating system for the processor, it enables the Operating system option.
If you are using the Eclipse IDE and set Processor to Generic/Custom, open the model Configuration Parameters and use the Hardware Implementation pane to define the custom hardware. With this approach, hardware support depends on the Simulink Coder product, not on the coder product. For more information, see Hardware Implementation Pane.
Clicking Add new opens a new dialog box where you specify configuration information for a processor that is not on the Processor list.
For details about the New Processor dialog box, refer to Add Processor Dialog Box.
Delete a processor that you added to the Processor list. You cannot delete any of the standard processors.
Enter the actual clock rate the board uses. This action does not change the rate on the board. Rather, the code generation process requires this information to produce code that runs correctly on the hardware. Setting this value incorrectly causes timing and profiling errors when you run the code on the hardware.
The timer uses the value of CPU clock to calculate the time for each interrupt. For example, a model with a sine wave generator block running at 1 kHz uses timer interrupts to generate sine wave samples at the proper rate. For example, using 100 MHz, the timer calculates the sine generator interrupt period as follows:
Sine block rate = 1 kHz, or 0.001 s/sample
CPU clock rate = 100 MHz, or 0.000000001 s/sample
To create sine block interrupts at 0.001 s/sample requires:
100,000,000/1000 = 1 Sine
block interrupt per 100,000 clock ticks
Select the following parameters and edit their values in the text box on the right:
Source files — Enter the full paths to source code files.
Include paths — Add paths to include files.
Libraries — Identify specific libraries for the processor. Required libraries appear on the list by default. To add more libraries, entering the full path to the library with the library file in the text area.
Initialize functions — If your project requires an initialize function, enter it in this field. By default, this parameter is empty.
Terminate functions — Enter a function to run when a program terminates. The default setting is not to include a specific termination function.
Note Invalid or incorrect entries in these fields can cause errors during code generation. When you enter a file path, library, or function, the block does not verify that the path or function exists or is valid. |
When entering a path to a file, library, or other custom code, use the following string in the path to refer to the IDE installation folder.
$(Install_dir)
Enter new paths or files (custom code items) one entry per line. Include the full path to the file for libraries and source code. Support options do not support functions that use return arguments or values. These parameters accept only functions of type void fname void as valid as entries.
You can also set up environment variables to use as folder path tokens. For example, if you set up an environment called USER_VAR, you can use it as a token when you define a path in your Target Preferences block. For example: $(USER_VAR)\myinstal\foo.c.
Select an operating system or RTOS for your target. If your target platform supports an operating system, the software enables the Operating system parameter. Otherwise, the software disables this option.
This button only appears when you are using Texas Instruments Code Composer Studio 3.3 IDE or Analog Devices VisualDSP++ IDE:
With Texas Instruments Code Composer Studio 3.3 IDE, the Get from IDE button imports the current Board Name and Processor Name from the IDE.
With Analog Devices VisualDSP++ IDE, the Get from IDE button imports the current Session Name and Processor Name from the IDE.
Use the Get from IDE button to ensure that the Target Preferences block, the IDE, and the hardware board all refer to the same processor. Otherwise, during code generation, the software generates a warning similar to the following message:
Target Preferences block specifies that the board named '<boardname1>' will be used to run generated code. However, since only board named '<boardname2>' is found in your system, that board will be used.
Board Name appears after you click Get from IDE. Select the board you are using. Match Board Name with the Board option near the top of the Board pane.
Processor Name appears after you click Get from IDE. If the board you selected in Board Name has multiple processors, select the processor you are using. MatchProcessor Name with the Processor option near the top of the Board pane.
After selecting a board, specify the layout of the physical memory on your processor and board to determine how to use it for your program. For supported boards, the board-specific Target Preferences blocks set the default memory map.
The Memory pane contains memory options for:
Physical Memory — Specifies the processor and board memory map
Cache Configuration — Select a cache configuration where available, such as L2 cache, and select one of the corresponding configuration options, such as 32 kb.
For more information about memory segments and memory allocation, consult the reference documentation for the IDE or processor.
The Physical Memory table shows the memory segments or memory banks available on the board and processor. By default, Target Preferences blocks show the memory segments found on the selected processor. In addition, the Memory pane on preconfigured Target Preferences blocks shows the memory segments available on the board, but external to the processor. Target Preferences blocks set default starting addresses, lengths, and contents of the default memory segments.
The default memory segments for each processor and board differ.
Click Add to add physical memory segments to the Memory banks table.
After you add the segment, you can configure the starting address, length, and contents for the new segment.
To change the memory segment name, click the name, and then type the new name. Names are case sensitive. NewSegment is not the same as newsegment or newSegment.
Address reports the starting address for the memory segment showing in Name. Address entries appear in hexadecimal format and are limited only by the board or processor memory.
From the starting address, Length sets the length of the memory allocated to the segment in Name. As in all memory entries, specify the length in hexadecimal format, in minimum addressable data units (MADUs).
For the C6000 processor family, the MADU requires inputs of 8 bytes, one word.
Configure the segment to store Code, Data, or Code & Data. Changing processors changes the options for each segment.
You can add and use as many segments of each type as you need, within the limits of the memory on your processor. Every processor must have a segment that holds code, and a segment that holds data.
Click Add to add a new memory segment to the processor memory map. When you click Add, a new segment name appears, for example NEWMEM1, in Name and on the Memory banks table. In Name, change the temporary name NEWMEM1 by entering the new segment name. Entering the new name, or clicking Apply, updates the temporary name on the table to the name you enter.
This option lets you remove a memory segment from the memory map. Select the segment to remove on the Memory banks table, and click Remove to delete the segment.
When the Processor on the Board pane supports a cache memory structure, the dialog box displays a table of Cache parameters. You can use this table to configure the cache as SRAM and partial cache. Both the data memory and the program share this second-level memory.
If your processor supports the two-level memory scheme, this option enables the L2 cache on the processor.
Some processors support code base memory organization. For example, you can configure part of internal memory as code.
Cache level lets you select one of the available cache levels to configure by selecting one of its configurations. For example, you can select L2 cache level, and choose one of its configurations, such as 32 kb.
Options on this pane specify where program sections appear in memory. Program sections differ from memory segments—sections comprise portions of the executable code stored in contiguous memory locations. Commonly used sections include .text, .bss, .data, and .stack. Some sections relate to the compiler, and some can be custom sections.
For more information about program sections and objects, refer to the online help for your IDE.
Within the Section pane, you configure the allocation of sections for Compiler and Custom needs.
This table provides brief definitions of the kinds of sections in the Compiler sections and Custom sections lists in the pane. All sections do not appear on all lists.
String | Section List | Description of the Section Contents |
|---|---|---|
.bss | Compiler | Static and global C variables in the code |
.cinit | Compiler | Tables for initializing global and static variables and constants |
.cio | Compiler | Standard I/O buffer for C programs |
.const | Compiler | Data defined with the C qualifier and string constants |
.data | Compiler | Program data for execution |
.far | Compiler | Variables, both static and global, defined as far variables |
.pinit | Compiler | Load allocation of the table of global object constructors section |
.stack | Compiler | The global stack |
.switch | Compiler | Jump tables for switch statements in the executable code |
.sysmem | Compiler | Dynamically allocated object in the code containing the heap |
.text | Compiler | Load allocation for the literal strings, executable code, and compiler generated constants |
You can learn more about memory sections and objects in the online help for your IDE.
When you highlight a section on the list, Description show a brief description of the section. Also, Placement shows you the memory allocation of the section.
Provides a brief explanation of the contents of the selected entry on the Compiler sections list.
Shows the allocation of the selected Compiler sections entry in memory. You change the memory allocation by selecting a different location from the Placement list. The list contains the memory segments as defined in the physical memory map on the Memory pane. Select one of the listed memory segments to allocate the highlighted compiler section to the segment.
To see a description of the placement item, hover your mouse pointer over the item for a few moments.
If your program uses code or data sections that are not in the Compiler sections, add the new sections to Custom sections.
This window lists data sections that are not in the Compiler sections.
With your new section added to the Name list, select the memory segment to which to add your new section. Within the restrictions imposed by the hardware and compiler, you can select any segment that appears on the list.
Clicking Add lets you configure a new entry to the list of custom sections. When you click Add, the block provides a new temporary name in Name. Enter the new section name to add the section to the Custom sections list. After typing the new name, click Apply to add the new section to the list. You can also click OK to add the section to the list and close the dialog box.
Enter the name of the new section here. To add a new section, click Add. Then, replace the temporary name with the name to use. Although the temporary name includes a period at the beginning you do not need to include the period in your new name. Names are case sensitive. NewSection is not the same as newsection, or newSection.
Identify whether the contents of the new section are Code, Data, or Any.
To remove a section from the Custom sections list, select the section and click Remove.
The DSP/BIOS pane is available if the two following conditions are true:
You are using Texas Instruments CCS IDE.
You set the Target Preferences block Processor option to a C6000 processors that support DSP/BIOS.
Selecting DSP/BIOS for Operating system on the Board pane enables this pane.
Use the Heap, Placement, and TSK task manager properties sections of this pane to configure various modules of DSP/BIOS.
For more information about tasks, refer to the Code Composer Studio online help.
The heap section contains the Create, Label, and Size options to manage the heap.
If your processor supports using a heap, selecting this option enables creating the heap. Define the heap using the Label and Size options. Create becomes unavailable for processors that do not provide a heap or do not allow you to configure the heap.
The location of the heap in the memory segment is not under your control. The only way to control the location of the heap in a segment is to make the segment and the heap the same size. Otherwise, the compiler determines the location of the heap in the segment.
After you select Create, this option lets you specify the size of the heap in words. Enter the number of words in decimal format. When you enter the heap size in decimal words, the system converts the decimal value to hexadecimal format. You can enter the value directly in hexadecimal format as well. Processors can support different maximum heap sizes.
Selecting Create enables this option. Enter your label for the heap in the Heap option.
Use the Data object and Code object options in Placement to configure the memory allocation of the selected Heap list entry.
Specify where to place new data objects in memory.
Specify where to place new code objects in memory.
Use the Default stack size (bytes), Stack segment for static tasks, and Stack segment for dynamic tasks options in TSK task manager properties to configure the task manager properties.
DSP/BIOS uses a stack to save and restore variables and CPU context during thread preemption for task threads. This option sets the size of the DSP/BIOS stack in bytes allocated for each task. The software sets the default value to 4096 bytes. You can set any size up to the limits for the processor. Set the stack size so that tasks do not use more memory than you allocate. Exceeding the stack memory size can cause the task to write into other memory or data areas, causing unpredictable behavior.
Use this option to specify where to allocate the stack for static tasks. Tasks that your program uses often are good candidates for static tasks. Infrequently used tasks usually work best as dynamic tasks.
The list offers IDRAM for locating the stack in memory. The Memory pane provides more options for the physical memory on the processor.
Like static tasks, dynamic tasks use a stack as well. Setting this option specifies where to locate the stack for dynamic tasks. In this case, MEM_NULL is the only valid stack location in memory. Allocate system heap storage to use this option. Specify the system heap configuration on the Memory Pane.
The Peripherals pane is only visible in Target Preference blocks configured for C2000 processors. This tabbed pane appears to configure peripheral settings and pin assignments.
To set the attributes for a peripheral, select the peripheral from the Peripherals list and then set the attribute options on the right side.
The following table describes all the peripherals provided on the Peripherals list. Some peripherals are not available on some C2000 processors.
| Peripheral Name | Description |
|---|---|
| ADC | Analog-to-Digital Converter (ADC) parameters |
| eCAN_A, eCAN_B | Enhanced Controller Area Network (eCAN) parameters for modules A or B |
| eCAP | Enhanced Capture (eCAP) parameters for pin mapping to GPIO |
| ePWM | Enhanced Pulse Width Modulation (ePWM) parameters for pin mapping to GPIO |
| I2C | Inter-Integrated Circuit (I2C) parameters for communications |
| SCI_A, SCI_B, SCI_C | Serial Communications Interface (SCI) parameters for communications with modules A, B, or C |
| SPI_A, SPI_B, SPI_C, SPI_D | Serial Peripheral Interface (SPI) parameters for communications with module A, B, C, or D |
| eQEP | Enhanced Quadrature Encoder Pulse (eQEP) parameters for pin mapping to GPIO |
| Watchdog | Watchdog enable/disable and timing |
| GPIO | General Purpose Input Output (GPIO) parameters for input qualification types |
| Flash_loader | Flash memory loader/programmer |
| DMA_ch[#] | Direct Memory Access (DMA) parameters for channels 1 to N |
| PLL | Phase Loop Lock (PLL) parameters to adjust clock settings and match custom oscillator frequencies |
| LIN | Local Interconnect Network (LIN) parameters for communications |
The high-speed peripheral clock (HSPCLK) controls the internal timing of the ADC module. The ADC derives the operating clock speed from the HSPCLK speed in several prescaler stages. For more information about configuring these scalers, refer to "Configuring ADC Parameters for Acquisition Window Width".
You can set the following parameters for the ADC clock prescaler:
This value does not actually have a direct effect on the core clock speed of the ADC. It serves to determine the width of the sampling or acquisition period. The higher the value, the wider is the sampling period. The default value is 4.
The HSPCLK speed is divided by this 4-bit value as the first step in deriving the core clock speed of the ADC. The default value is 3.
After dividing the HSPCLK speed by the ADCLKPS value, setting the CPS parameter to 1, the default value, divides the result by 2.
By default, an internally generated band gap voltage reference supplies the ADC logic. However, depending on application requirements, you can enable External reference so the ADC logic uses an external voltage reference instead. Select the checkbox to use a 2.048V external voltage reference.
The 280x ADC supports offset correction via a 9-bit value that it adds or subtracts before the results are available in the ADC result registers. Timing for results is not affected. The default value is 0.
(For Piccolo processors) When you disable the External reference option, the ADC logic uses a fixed 0-volt to 3.3-volt input range and the software disables VREFHI and VREFLO. To interpret the ADC input as a ratiometric signal, select the External reference option. Then set values for the high voltage reference (VREFHI) and the low voltage reference (VREFLO). VREFHI uses the external ADCINA0 pin, and VREFLO uses the internal GND.
(For Piccolo processors) Use this option to configure when the ADC sets ADCINTFLG .ADCINTx relative to the SOC and EOC Pulses. Select Late interrupt pulse or Early interrupt pulse.
(For Piccolo processors) Use this option to enable and configure SOC high priority mode . In All in round robin mode, the default selection, the ADC services each SOC interrupt in a numerical sequence.
Choose one of the high priority selections to assign high priority to one or more of the SOCs. In this mode, the ADC operates in round robin mode until it receives a high priority SOC interrupt. The ADC finishes servicing the current SOC, services the high priority SOCs, and then returns to the next SOC in the round robin sequence.
For example, the ADC is servicing SOC8 when it receives a high priority interrupt on SOC1. The ADC completes servicing SOC8, services SOC1, and then services SOC9.
(For Piccolo processors) Select the pin to which the ADC sends the XINT2SOC pulse.
For more help on setting the timing parameters for the eCAN modules, refer to Configuring Timing Parameters for CAN Blocks. You can set the following parameters for the eCAN module:
Value by which to scale the bit rate. Valid values are from 1 to 256.
To enable time-stamping and to use Mailbox Numbers 16 through 31 in the C2000 eCAN blocks, enable this parameter. Texas Instruments documentation refers to this "HECC mode".
Number of samples used by the CAN module to determine the CAN bus level. Selecting Sample_one_time samples once at the sampling point. Selecting Sample_three_times samples once at the sampling point and twice before at a distance of TQ/2. The CAN module makes a majority decision from the three points.
Sets the message resynchronization triggering. Options are Only_falling_edges and Both_falling_and_rising_edges.
Sets the synchronization jump width, which determines how many units of TQ a bit can be shortened or lengthened when resynchronizing.
If you set this parameter to True, the eCAN module goes to loopback mode. Loopback mode sends a "dummy" acknowledge message back without needing an acknowledge bit. The default is False.
Sets the value of time segment 1, which, with TSEG2 and Baud rate prescaler, determines the length of a bit on the eCAN bus. Valid values for TSEG1 are from 1 through 16.
Sets the value of time segment 2, which, with TSEG1 and Baud rate prescaler, determines the length of a bit on the eCAN bus. Valid values for TSEG2 are from 1 through 8.
Assigns the CAN receive pin to use with the eCAN_B module. Possible values are GPIO10, GPIO13, GPIO17, and GPIO21.
Assigns the CAN transmit pin to use with the eCAN_B module. Possible values are GPIO8, GPIO12, GPIO16, and GPIO20.
Assigns eCAP pins to GPIO pins if necessary.
Select an option from the list—None, GPIO5, or GPIO24.
Select an option from the list—None, GPIO7, or GPIO25.
Select an option from the list—None, GPIO9, or GPIO26.
Select an option from the list—None, GPIO11, or GPIO27.
Assigns ePWM signals to GPIO pins, if necessary.
Assigns the ePWM external sync pulse input (SYNCI) to a GPIO pin. Choices are None (the default), GPIO6, and GPIO32.
Assigns the ePWM external sync pulse output (SYNCO) to a GPIO pin. Choices are None (the default), GPIO6, and GPIO33.
Assigns the trip-zone input 2 (TZ2) to a GPIO pin. Choices are None (the default), GPIO16, and GPIO28.
Assigns the trip-zone input 3 (TZ3) to a GPIO pin. Choices are None (the default), GPIO17, and GPIO29.
Assigns the trip-zone input 5 (TZ5) to a GPIO pin. Choices are None (the default), GPIO16, and GPIO28.
Assigns the trip-zone input 6 (TZ6) to a GPIO pin. Choices are None (the default), GPIO17, and GPIO29.
Report or set Inter-Integrated Circuit parameters. For more information, consult the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A, available on the Texas Instruments Web site.
Configure the I2C module as Master or Slave.
If a module is an I2C master, it:
Initiates communication with slave nodes by sending the slave address and requesting data transfer to or from the slave.
Outputs the Master clock frequency on the serial clock line (SCL) line.
If a module is an I2C slave, it:
Synchronizes itself with the serial clock line (SCL) line.
Responds to communication requests from the master.
When Mode is Slave, you can configure the Addressing format, Address register, and Bit count parameters.
The Mode parameter corresponds to bit 10 (MST) of the I2C Mode Register (I2CMDR).
If Mode is Slave, determine the addressing format of the I2C master, and set the I2C module to the same mode:
7-Bit Addressing, the normal address mode.
10-Bit Addressing, the expanded address mode.
Free Data Format, a mode that does not use addresses. (If you Enable loopback, the Free data format is not supported.)
The Addressing format parameter corresponds to bit 3 (FDF) and bit 8 (XA) of the I2C Mode Register (I2CMDR).
If Mode is Slave, enter the 7-bit (0–127) or 10-bit (0–1023) address this I2C module uses while it is a slave.
This parameter corresponds to bits 9–0 (OAR) of the I2C Own Address Register (I2COAR).
If Mode is Slave, set the number of bits in each data byte the I2C module transmits and receives. This value must match that of the I2C master.
This parameter corresponds to bits 2–0 (BC) of the I2C Mode Register (I2CMDR).
This field displays the frequency the I2C module uses internally. To set this value, change the Module clock prescaler. For more information about this value, consult the "Formula for the Master Clock Period" section in the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721, available on the Texas Instruments Web site.
This field displays the master clock frequency. For more information about this value, consult the "Clock Generation" section in the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721, available on the Texas Instruments Web site.
If Mode is Master, configure the module clock frequency by entering a value 0–255.
Module clock frequency = I2C input clock frequency / (Module clock prescaler + 1)
The I2C specifications require a module clock frequency between 7 MHz and 12 MHz.
The I2C input clock frequency depends on the DSP input clock frequency and the value of the PLL Control Register divider (PLLCR). For more information on setting the PLLCR, consult the documentation for your specific Digital Signal Controller.
This Module clock prescaler corresponds to bits 7–0 (IPSC) of the I2C Prescaler Register (I2CPSC).
When Mode is Master, this divider determines the duration of the low state of the SCL line on the I2C-bus.
The low-time duration of the master clock = Tmod x (ICCL + d).
For more information about this value, consult the "Formula for the Master Clock Period" section in the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A, available on the Texas Instruments Web site.
This parameter corresponds to bits 15–0 (ICCL) of the Clock Low-Time Divider Register (I2CCLKL).
When Mode is Master, this divider determines the duration of the high state on the serial clock pin (SCL) of the I2C-bus.
The high-time duration of the master clock = Tmod x (ICCL + d).
For more information about this value, consult the "Formula for the Master Clock Period" section in the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A, available on the Texas Instruments Web site.
This parameter corresponds to bits 15–0 (ICCH) of the Clock High-Time Divider Register (I2CCLKH).
When Mode is Master, enable or disable digital loopback mode. In digital loopback mode, I2CDXR transmits data over an internal path to I2CDRR, which receives the data after a configurable delay. The delay, measured in DSP cycles, equals (I2C input clock frequency/module clock frequency) x 8.
While Enable loopback is enabled, free data format addressing is not supported.
This parameter corresponds to bit 6 (DLB) of the I2C Mode Register (I2CMDR).
This parameter corresponds to bit 5 (TXFFIENA) of the I2C Transmit FIFO Register (I2CFFTX).
This parameter corresponds to bits 4–0 (TXFFIL4-0) of the I2C Transmit FIFO Register (I2CFFTX).
This parameter corresponds to bit 5 (RXFFIENA) of the I2C Receive FIFO Register (I2CFFRX).
This parameter corresponds to bit 4–0 (RXFFIL4-0) of the I2C Receive FIFO Register (I2CFFRX).
Select this parameter to display and individually configure the following five Basic I2C Interrupt Request parameters in the Interrupt Enable Register (I2CIER):
Enable AAS interrupt
Enable SCD interrupt
Enable ARDY interrupt
Enable NACK interrupt
Enable AL interrupt
Enable the addressed-as-slave interrupt.
When enabled, the I2C module generates an interrupt (AAS bit = 1) upon receiving one of the following:
Its Own address register
A general call (all zeros)
A data byte is in free data format
When enabled, the I2C module clears the interrupt (AAS = 0) upon receiving one of the following:
Multiple START conditions (7-bit addressing mode only)
A slave address that is different from Own address register (10-bit addressing mode only)
A NACK or a STOP condition
This parameter corresponds to bit 6 (AAS) of the Interrupt Enable Register (I2CIER).
Enable stop condition detected interrupt.
When enabled, the I2C module generates an interrupt (SCD bit = 1) when the CPU detects a stop condition on the I2C bus.
When enabled, the I2C module clears the interrupt (SCD = 0) upon one of the following events:
The CPU reads the I2CISRC while it indicates a stop condition
A reset of the I2C module
Someone manually clears the interrupt
This parameter corresponds to bit 5 (SCD) of the Interrupt Enable Register (I2CIER).
Enable register-access-ready interrupt enable bit.
When enabled, the I2C module generates an interrupt (ARDY bit = 1) when the previous address, data, and command values in the I2C module registers have been used and new values can be written to the I2C module registers.
This parameter corresponds to bit 2 (ARDY) of the Interrupt Enable Register (I2CIER).
Enable no-acknowledgment interrupt enable bit.
When enabled, the I2C module generates an interrupt (NACK bit = 1) when the module is a transmitter in master or slave mode and it receives a NACK condition.
This parameter corresponds to bit 1 (NACK) of the Interrupt Enable Register (I2CIER).
Enable arbitration-lost interrupt.
When enabled, the I2C module generates an interrupt (AL bit = 1) when the I2C module is operating as a master transmitter and looses an arbitration contest with another master transmitter.
This parameter corresponds to bit 0 (AL) of the Interrupt Enable Register (I2CIER).
The serial communications interface parameters you can set for module A. These parameters are:
Baud rate for transmitting and receiving data. Select from 115200 (the default), 57600, 38400, 19200, 9600, 4800, 2400, 1200, 300, and 110.
If this option is set to True, system waits until data is available to read (when data length is reached). If this option is set to False, system checks FIFO periodically (in polling mode) to see if there is any data to read. If data is present, it reads and outputs the contents. If no data is present, it outputs the last value and continues.
Length in bits of each transmitted or received character, set to 8 bits.
Select Raw_data or Protocol mode. Raw data is unformatted and sent whenever the transmitting side is ready to send, whether the receiving side is ready or not. No deadlock condition can occur because there is no wait state. Data transmission is asynchronous. With this mode, it is possible the receiving side could miss data, but if the data is noncritical, using raw data mode can avoid blocking any processes.
When you select protocol mode, some handshaking between host and processor occurs. The transmitting side sends $SND to indicate it is ready to transmit. The receiving side sends back $RDY to indicate it is ready to receive. The transmitting side then sends data and, when the transmission is completed, it sends a checksum.
Advantages to using protocol mode include:
Avoids deadlock
Ensures that data is received correctly (checksum)
Ensures that data is received by processor
Ensures time consistency; each side waits for its turn to send or receive
Select Little Endian or Big Endian, to match the endianness of the data being moved.
Select 8_bits or 16_bits, to match the width of the data being moved by the data swap operation. When you set Data byte order to Big Endian, the only available option for Data swap width is 8_bits.
Select this parameter to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, a C28x DSP Tx pin is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Select whether to use 1 or 2 stop bits.
Type of parity to use. Available selections are None, Odd parity, or Even parity. None disables parity. Odd sets the parity bit to one if you have an odd number of ones in your bytes, such as 00110010. Even sets the parity bit to one if you have an even number of ones in your bytes, such as 00110011.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive/transmit sequence is complete. Free_run continues running regardless of the breakpoint.
Assigns the SCI receive pin to use with the SCI module.
Assigns the SCI transmit pin to use with the SCI module.
The serial peripheral interface parameters you can set for the A module. These parameters are:
To set the Baud rate factor, search for "Baud Rate Determination" and "SPI Baud Rate Register (SPIBRR) Bit Descriptions" in TMS320x28xx, 28xxx DSP Serial Peripheral Interface (SPI) Reference Guide, Literature Number: SPRU059, available on the Texas Instruments Web Site.
Select No_delay or Delay_half_cycle.
Select Rising_edge or Falling_edge.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the selected suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive or transmit sequence is complete. Free_run continues running regardless of the breakpoint.
Length in bits from 1 to 16 of each transmitted or received character. For example, if you select 8, the maximum data that can be transmitted using SPI is 28-1. If you send data greater than this value, the buffer overflows.
Select this option to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, the Tx pin on a C28x DSP is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Enable SPI communication over three pins instead of the normal four pins.
Set true or false.
Set level for receive FIFO interrupt. Select 0 through 16.
Set level for transmit FIFO interrupt. Select 0 through 16.
Enter FIFO transmit delay (in processor clock cycles) to pause between data transmissions. Enter an integer.
Set to Master or Slave.
Assigns the SPI something (CLK) to a GPIO pin. Choices are None (default), GPI014, or GPI026.
Assigns the SPI something (SOMI) to a GPIO pin. Choices are None (default), GPI013, or GPI025.
Assigns the SPI something (STE) to a GPIO pin. Choices are None (default), GPI015, or GPI027.
Assigns the SPI something (SIMO) to a GPIO pin. Choices are None (default), GPI012, or GPI024.
Assigns eQEP pins to GPIO pins.
Select an option from the list—GPIO20 or GPIO50.
Select an option from the list—GPIO21 or GPIO51.
Select an option from the list—GPIO22 or GPIO52.
Select an option from the list—GPIO23 or GPIO53.
When enabled, if the software fails to reset the watchdog counter within a specified interval, the watchdog resets the processor or generates an interrupt. This feature enables the processor to recover from some fault conditions.
For more information, locate the Data Manual or System Control and Interrupts Reference Guide for your processor on the Texas Instruments Web site.
Enable the watchdog timer module.
This parameter corresponds to bit 6 (WDDIS) of the Watchdog Control Register (WDCR) and bit 0 (WDOVERRIDE) of the System Control and Status Register (SCSR).
Set the watchdog timer period relative to OSCCLK/512.
This parameter corresponds to bits 2–0 (WDPS) of the Watchdog Control Register (WDCR).
This field displays the timer period in seconds. This value automatically updates when you change the Counter clock parameter.
Configure the watchdog to reset the processor or generate an interrupt when the software fails to reset the watchdog counter:
Select Chip reset to generate a signal that resets the processor (WDRST signal) and disable the watchdog interrupt signal (WDINT signal).
Select Raise WD Interrupt to generate a watchdog interrupt signal (WDINT signal) and disable the reset processor signal (WDRST signal). This signal can be used to wake the device from an IDLE or STANDBY low-power mode.
This parameter corresponds to bit 1 (WDENINT) of the System Control and Status Register (SCSR).
Each pin selected for input offers three signal qualification types:
Sync to SYSCLKOUT — This setting is the default for all pins at reset. Using this qualification type, the input signal is synchronized to the system clock SYSCLKOUT. The following figure shows the input signal measured on each tick of the system clock, and the resulting output from the qualifier.
Qualification using 3 samples — This setting requires three consecutive cycles of the same value for the output value to change. The following figure shows that, in the third cycle, the GPIO value changes to 0, but the qualifier output is still 1 because it waits for three consecutive cycles of the same GPIO value. The next three cycles all have a value of 0, and the output from the qualifier changes to 0 immediately after the third consecutive value is received.
Qualification using 6 samples — This setting requires six consecutive cycles of the same GPIO input value for the output from the qualifier to change. In the following figure, the glitch A has no effect on the output signal. When the glitch occurs, the counting begins, but the next measurement is low again, so the count is ignored. The output signal does not change until six consecutive samples of the high signal are measured.
Qualification sampling period prescaler
Visible only when an appropriate setting for Qualification type for GPIO [pin#] is selected. The qualification sampling period prescaler, with possible values of 0 to 255, calculates the frequency of the qualification samples or the number of system clock ticks per sample. The formula for calculating the qualification sampling frequency is SYSCLKOUT/(2 * Prescaler), except for zero. When Qualification sampling period prescaler=0, a sample is taken every SYSCLKOUT clock tick. For example, a prescale setting of 0 means that a sample is taken on each SYSCLKOUT tick.
The following figure shows the SYSCLKOUT ticks, a sample taken every clock tick, and the Qualification type set to Qualification using 3 samples. In this case, the Qualification sampling period prescaler=0:
In the next figure Qualification sampling period prescaler=1. A sample is taken every two clock ticks, and the Qualification type is set to Qualification using 3 samples. The output signal changes much later than if Qualification sampling period prescaler=0.
In the following figure, Qualification sampling period prescaler=2. Thus , a sample is taken every four clock ticks, and the Qualification type is set to Qualification using 3 samples.
You can use Flash_loader to:
Automatically program generated code to flash memory on the target when you build the code.
Manually erase, program, or verify specific flash memory sectors.
To use this feature, download and install the appropriate TI Flash API plugin from the TI Web site.
For more information, consult the Programming Flash Memory topic or the *_API_Readme.pdf file included in the TI Flash API downloadable zip file.
Enable the flash programmer by selecting a task for it to perform when you click Execute or build the software. To program the flash memory when you build the software, select Erase, Program, Verify.
When enabled, the flash programmer erases all of the flash sectors defined by the COFF file.
Specify the folder path of the TI flash API executable you downloaded and installed on your computer. Use Browse to locate the file or enter the path in the text box.
Click this button to initiate the task selected in Enable Flash Programmer.
The Direct Memory Access module transfers data directly between peripherals and memory using a dedicated bus, increasing overall system performance.
You can individually enable and configure each DMA channel.
The DMA module services are event driven. Using the Interrupt source and External pin (GPIO) parameters, you can configure a wide range of peripheral interrupt event triggers.
To use DMA with the C280x/C28x3x ADC block, open the ADC block, enable Use DMA (with C28x3x), and select a DMA channel number. To avoid error messages, open the Target Preferences block > Peripherals and disable the same DMA channel number.
For more information, consult the TMS320x2833x, 2823x Direct Memory Access (DMA) Module Reference Guide, Literature Number: SPRUFB8A, and the Increasing Data Throughput using the TMS320F2833x DSC DMA training presentation (requires login), both available from the TI Web site.
Enable this parameter to edit the configuration of a specific DMA channel.
If your model includes an ADC block with the Use DMA (with C28x3x) parameter enabled, disable the same DMA channel here in the Target Preferences block.
This parameter has no corresponding bit or register.
Select the size of the data bit transfer: 16 bit or 32 bit.
The DMA read/write data buses are 32 bits wide. 32-bit transfers have twice the data throughput of a 16-bit transfer.
When providing DMA service to McBSP, set Data size to 16 bit.
The following parameters are based on a 16-bit word size. If you set Data size to 32 bit, double the value of the following parameters:
Size: Burst
Source: Burst step
Source: Transfer step
Source: Wrap step
Destination: Burst step
Destination: Transfer step
Destination: Wrap step
Data size corresponds to bit 14 (DATASIZE) in the Mode Register (MODE).
Select the peripheral interrupt that triggers a DMA burst for the specified channel.
Selecting SEQ1INT or SEQ2INT generates a message: "Use ADC block to implement the DMA function." To do so, open the ADC block, select the Use DMA (with C28x3x) parameter, select a DMA channel, and disable the same DMA channel in the Target Preferences block. Currently, when you use the ADC block to implement DMA, the corresponding DMA channel settings are not configurable in the Target Preferences block.
Select XINT1, XINT2, or XINT13 to configure GPIO pin 0 to 31 as an external interrupt source. Select XINT3 to XINT7 to configure GPIO pin 32 to 63 as an external interrupt source. For more information about configuring XINT, consult the following references:
TMS320x2833x, 2823x External Interface (XINTF) User's Guide, Literature Number: SPRU949, available on the TI Web site.
TMS320x2833x System Control and Interrupts, Literature Number: SPRUFB0, available on the TI Web site.
The C280x/C2802x/C2803x/C28x3x/c2834x GPIO Digital Input and C280x/C2802x/C2803x/C28x3x/c2834x GPIO Digital Output block reference sections.
Currently, Interrupt source does not support items TINT0 through MREVTB in the drop-down menu.
The Interrupt source parameter corresponds to bit 4-0 (PERINTSEL) in the Mode Register (MODE).
When you set Interrupt source is set to an external interface (XINT[#]), specify the GPIO pin number from which the interrupt originates.
This parameter corresponds to the GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers. For more information, consult the TMS320x2833x System Control and Interrupts Reference Guide, Literature Number SPRUFB0, available from the TI Web site.
Specify the number of bursts before returning the current source address pointer to the Source Begin Address value. To disable wrapping, enter a value for SRC wrap that is greater than the Transfer value.
This parameter corresponds to bits 15-0 (SRC_WRAP_SIZE) in the Source Wrap Size Register (SRC_WRAP_SIZE).
Specify the number of bursts before returning the current destination address pointer to the Destination Begin Address value. To disable wrapping, enter a value for DST wrap that is greater than the Transfer value.
This parameter corresponds to bits 15-0 (DST_WRAP_SIZE) in the Destination Wrap Size Register (DST_WRAP_SIZE).
Set the starting address for the current source address pointer. The DMA module points to this address at the beginning of a transfer and returns to it as specified by the SRC wrap parameter.
This parameter corresponds to bits 21-0 (BEGADDR) in the Active Source Begin Register (SRC_BEG_ADDR).
Set the starting address for the current destination address pointer. The DMA module points to this address at the beginning of a transfer and returns to it as specified by the DST wrap parameter.
This parameter corresponds to bits 21-0 (BEGADDR) in the Active Destination Begin Register (DST_BEG_ADDR).
Note When you select Use DMA (with C28x3x) in the C280x/C28x3x ADC block, the value of the destination Begin address (dstAdd) is the ADC buffer address (ADCbufadr) minus the Number of conversions (NoC) in the ADC block. In other words, dstAdd = ADCbufadr – NoC.
For example, when you enable Use DMA (with C28x3x) for a F28232 target, the DMA module sets the destination Begin address to 0xDFF9 (57337) because the ADCbufadr 57340 (0xDFFC) minus 3 conversions equals 57337 (0xDFF9). |
Specify the number of 16-bit words in a burst, from 1 to 32. The DMA module must complete a burst before it can service the next channel.
Set the Burst value appropriately for the peripheral the DMA module is servicing. For the ADC, the value equals the number of ADC registers used, up to 16. For multichannel buffered serial ports (McBSP), which lack FIFOs, the value is 1. For RAM, the value can range from 1 to 32.
This parameter corresponds to bits 4-0 (BURSTSIZE) in the Burst Size Register (BURST_SIZE).
Note This parameter is based on a 16-bit word size. If you set Data size to 32 bit, double the value of this parameter. |
Note When you select Use DMA (with C28x3x) in the C280x/C28x3x ADC block, the value assigned to Burst equals the ADC block Number of conversions (NOC) multiplied by a value for the ADC block Conversion mode (CVM). Burst = NOC * CVM If Conversion mode is Sequential, CVM = 1. If Conversion mode is Simultaneous, CVM = 2. For example, Burst = 6 if NOC = 3 and CVM = 2 (6 = 3 * 2). |
Specify the number of bursts in a transfer, from 1 to 65536.
This parameter corresponds to bits 15-0 (TRANSFERSIZE) in the Transfer Size Register (TRANSFER_SIZE).
Set the number of 16-bit words by which to increment or decrement the current address pointer before the next burst. Enter a value from –4096 (decrement) to 4095 (increment).
To disable incrementing or decrementing the address pointer, set Burst step to 0. For example, because McBSP does not use FIFO, configure DMA to maintain the correct sequence of the McBSP data by moving each word of the data individually. Accordingly, when you use DMA to transmit or receive McBSP data, set Burst size to 1 word and Burst step to 0.
This parameter corresponds to bits 15-0 (SRCBURSTSTEP) in the Source Burst Step Size Register (SRC_BURST_STEP).
Set the number of 16-bit words by which to increment or decrement the current address pointer before the next burst. Enter a value from –4096 (decrement) to 4095 (increment).
To disable incrementing or decrementing the address pointer, set Burst step to 0. For example, because McBSP does not use FIFO, configure DMA to maintain the correct sequence of the McBSP data by moving each word of the data individually. Accordingly, when you use DMA to transmit or receive McBSP data, set Burst size to 1 word and Burst step to 0.
This parameter corresponds to bits 15-0 (DSTBURSTSTEP) in the Destination Burst Step Size Register (DST_BURST_STEP).
Set the number of 16-bit words by which to increment or decrement the current address pointer before the next transfer. Enter a value from –4096 (decrement) to 4095 (increment).
To disable incrementing or decrementing the address pointer, set Transfer step to 0.
This parameter corresponds to bits 15-0 (SRCTRANSFERSTEP) Source Transfer Step Size Register (SRC_TRANSFER_STEP).
If DMA is configured to perform memory wrapping (if SRC wrap is enabled) the corresponding source Transfer step has no effect.
Set the number of 16-bit words by which to increment or decrement the current address pointer before the next transfer. Enter a value from –4096 (decrement) to 4095 (increment).
To disable incrementing or decrementing the address pointer, set Transfer step to 0.
This parameter corresponds to bits 15-0 (DSTTRANSFERSTEP) Destination Transfer Step Size Register (DST_TRANSFER_STEP).
If DMA is configured to perform memory wrapping (if DST wrap is enabled) the corresponding destination Transfer step has no effect.
Set the number of 16-bit words by which to increment or decrement the SRC_BEG_ADDR address pointer when a wrap event occurs. Enter a value from –4096 (decrement) to 4095 (increment).
This parameter corresponds to bits 15-0 (WRAPSTEP) in the Source Wrap Step Size Registers (SRC_WRAP_STEP).
Set the number of 16-bit words by which to increment or decrement the DST_BEG_ADDR address pointer when a wrap event occurs. Enter a value from –4096 (decrement) to 4095 (increment).
This parameter corresponds to bits 15-0 (WRAPSTEP) in the Destination Wrap Step Size Registers (DST_WRAP_STEP).
Enable this parameter to have the DMA channel send an interrupt to the CPU via the PIE at the beginning or end of a data transfer.
This parameter corresponds to bit 15 (CHINTE) and bit 9 (CHINTMODE) in the Mode Register (MODE).
Enable this parameter to have the DMA channel complete an entire transfer in response to an interrupt event trigger. This option allows a single DMA channel and peripheral to dominate resources, and may streamline processing, but it also creates the potential for resource conflicts and delays.
Disable this parameter to have DMA complete one burst per channel per interrupt.
When Interrupt source is set to SEQ1INT, enable this parameter to reset the DMA wrap counter when it receives the ADCSYNC signal from SEQ1INT. This ensures that the wrap counter and the ADC channels remain synchronized with each other.
If Interrupt source is not set to SEQ1INT, Sync enable has no effect.
This parameter corresponds to bit 12 (SYNCE) of the Mode Register (MODE).
Select this parameter to leave the DMA channel enabled upon completing a transfer. The channel will wait for the next interrupt event trigger.
Clear this parameter to disable the DMA channel upon completing a transfer. The DMA module disables the DMA channel by clearing the RUNSTS bit in the CONTROL register when it completes the transfer. To use the channel again, first reset the RUN bit in the CONTROL register.
When Sync enable is enabled, enabling this parameter resets the destination wrap counter (DST_WRAP_COUNT) when the DMA module receives the SEQ1INT interrupt/ADCSYNC signal. Disabling this parameter resets the source wrap counter (SCR_WRAP_COUNT) when the DMA module receives the SEQ1INT interrupt/ADCSYNC signal.
This parameter is associated with bit 13 (SYNCSEL) in the Mode Register (MODE).
This parameter is only available for DMA_ch1.
Enable this setting when DMA channel 1 is configured to handle high-bandwidth data, such as ADC data, and the other DMA channels are configured to handle lower-priority data.
When enabled, the DMA module services each enabled channel sequentially until it receives a trigger from channel 1. Upon receiving the trigger, DMA interrupts its service to the current channel at the end of the current word, services the channel 1 burst that generated the trigger, and then continues servicing the current channel at the beginning of the next word.
Disable this channel to give each DMA channel equal priority, or if DMA channel 1 is the only enabled channel.
When disabled, the DMA module services each enabled channel sequentially.
This parameter corresponds to bit 0 (CH1PRIORITY) in the Priority Control Register 1 (PRIORITYCTRL1).
Enable this parameter to have the DMA channel send an interrupt to the CPU via PIE if the DMA module receives a peripheral interrupt while a previous interrupt from the same peripheral is waiting to be serviced.
This parameter is typically used for debugging during the development phase of a project.
The Enable overflow interrupt parameter corresponds to bit 7 (OVRINTE) of the Mode Register (MODE), and involves the Overflow Flag Bit (OVRFLG) and Peripheral Interrupt Trigger Flag Bit (PERINTFLG).
The default PLL register values run the CPU clock (CLKIN) at its maximum frequency. The parameters assume that the external oscillator frequency on the board (OSCCLK) is the one recommended by the processor vendor.
Change the PLL settings if:
You want to change the CPU frequency.
The external oscillator frequency differs from the value recommended by the manufacturer.
Use the following equation to determine the CPU frequency (CLKIN):
CLKIN = (OSCCLK * PLLCR) / (DIVSEL or CLKINDIV)
Where:
CLKIN is the frequency at which the CPU operates, also known as the CPU clock.
OSCCLK is the frequency of the oscillator.
PLLCR is the PLL Control Register value.
CLKINDIV is the "Clock in Divider".
DIVSEL is the "Divider Select".
The availability of the DIVSEL or CLKINDIV parameters change depending on the selected processor. If neither parameter is available, use the following equation instead:
CLKIN = (OSCCLK * PLLCR) / 1
Enter the resulting CPU clock frequency (CLKIN) in the CPU clock parameter of the Target Preferences block.
For more information, consult the "PLL-Based Clock Module" section in the Texas Instruments Reference Guide for your processor.
For detailed information on the LIN module, see TMS320F2803x Piccolo Local Interconnect Network (LIN) Module, Literature Number SPRUGE2, available at the Texas Instruments Web site.
The following options configure all LIN Transmit and LIN Receive blocks within a model.
To enable LIN loopback testing, select this option. While this option is enabled, the LIN module does the following:
Internally redirects the LINTX output to the LINRX input.
Puts the external LINTX pin into high state.
Puts the external LINRX pin into a high impedance state.
The default is disabled (unchecked).
Use this option to configure how the LIN state machine behaves while you debug the program on an emulator. If you select Hard_abort, entering LIN debug mode halts the transmissions and counters. The transmissions and counters resume when you exit LIN debug mode. If you select Free_run, entering LIN debug mode allows the current transmit and receive functions to complete.
The default is Free_run.
Use this option to configure parity checking:
To disable parity checking, select None.
To enable odd parity checking, select Odd.
To enable even parity checking, select Even.
The default is None.
In order for ID parity error interrupt in the LIN Receive block to generate interrupts, also enable Parity mode.
Set the number of data bytes in the response field, from 1 to 8 bytes.
The default is 8 bytes.
To set the LIN baud rate manually, enter a prescaler value, from 0 to 16777215. Click Apply to update the Baud rate display.
The default is 15.
For more information, consult the "Baud Rate" topic in the TI document, TMS320F2803x Piccolo Local Interconnect Network (LIN) Module, Literature Number SPRUGE2.
To set the LIN baud rate manually, enter a fractional divider value, from 0 to 15. Click Apply to update the Baud rate display.
The default is 4.
For more information, consult the "Baud Rate" topic in the TI document, TMS320F2803x Piccolo Local Interconnect Network (LIN) Module, Literature Number SPRUGE2.
This field displays the baud rate. For more information, see "Setting the LIN baud rate".
Enable or disable the LIN module from using the ID-field bits ID4 and ID5 for length control.
The default is ID4 and ID5 not used for length control
Set the "endianness" of the LIN message data bytes to Little_Endian or Big_Endian.
The default is Little_Endian.
Select 8_bits or 16_bits. If you set Data byte order to Big_Endian, the only available option for Data swap width is 8_bits.
Map the LINTX output to a specific GPIO pin.
The default is GPIO9.
Map the LINRX input to a specific GPIO pin.
The default is GPIO11.
Put the LIN module in Master or Slave mode. The default is Slave.
In master mode, the LIN node can transmit queries and commands to slaves. In slave mode, the LIN module responds to queries or commands from a master node.
This option corresponds to the CLK_MASTER field in the SCI Global Control Register (SCIGCR1).
Select which type of mask filtering comparison the LIN module performs, ID byte or ID slave task byte.
If you select ID byte, the module uses the RECID and ID-BYTE fields in the LINID register to detect a match. If you select this option and enter 0xFF for LINMASK, the LIN module never reports matches.
I you select ID slave task. the module uses the RECID an ID-SlaveTask byte to detect a match. If you select this option and enter 0xFF for LINMASK, the LIN module always reports matches.
The default is ID slave task byte.
If you set ID filtering to ID byte, use this option to set the ID BYTE, also known as the "LIN mode message ID". In master mode, the CPU writes this value to initiate a header transmission. In slave mode, the LIN module uses this value to perform message filtering.
The default is 0x3A.
If you set ID filtering to ID slave task byte, use this option to set the ID-SlaveTask BYTE. The LIN node compares this byte with the Received ID and determines whether to send a transmit or receive response.
The default is 0x30.
Use this option to select the appropriate type of checksum. If you select Classic, the LIN node generates the checksum field from the data fields in the response. If you select Enhance, the LIN node generates the checksum field from both the ID field in the header and data fields in the response. LIN 1.3 supports classic checksums only. LIN 2.0 supports both classic and enhanced checksums.
The default is Classic.
When you enable (select) this checkbox, the LIN node uses transmit and receive buffers instead of just one register. This setting affects various other LIN registers, such as: checksums, framing errors, transmitter empty flags, receiver ready flags, transmitter ready flags.
The default is enabled (checked).
The dialog box displays this option when you set LIN mode to Slave.
If you enable this option, the slave node automatically adjusts its baud rate to match that of the master node. For this feature to work correctly, first set the Baud rate prescaler and Baud rate fractional divider.
If you disable this option, the LIN module sets a static baud rate based on the Baud rate prescaler and Baud rate fractional divider.
The default is disabled (unchecked).
The dialog box displays this option when you set LIN mode to Slave.
If you enable this option, the slave node generates interrupts when it detects irregularities in the synch field. This option is only relevant if you enable Enable adapt mode.
The default is Disabled.
The dialog box displays this option when you set LIN mode to Slave.
If you enable this option, the LIN module generates an interrupt if it does not receive a complete response from the master node within an appropriate timeframe.
The default is Disabled.
The dialog box displays this option when you set LIN mode to Slave.
When enabled, the slave node generates an interrupt when it sends three wakeup signals to the master node and does not receive a header in response. (The slave waits 1.5 seconds before sending another series of wakeup signals.) This interrupt typically indicates the master node is having a problem recovering from low-power or sleep mode.
The default is Disabled.
The dialog box displays this option when you set LIN mode to Slave.
When enabled, the slave node generates an interrupt when it sends a wakeup signal to the master node and does not receive a header in response. (The slave waits 150 milliseconds before sending another series of wakeup signals.) This interrupt typically indicates the master node is delayed recovering from low-power or sleep mode.
The default is Disabled.
The dialog box displays this option when you set LIN mode to Slave.
When enabled, the slave node generates an interrupt after 4 seconds of inactivity on the LIN bus.
The default is Disabled.
The dialog box displays this option when you set LIN mode to Slave.
When you enable this option:
In low-power mode, a LIN slave node generates a wakeup interrupt when it detects the falling edge of a wake-up pulse or a low level on the LINRX pin.
A LIN slave node that is "awake" generates a wakeup interrupt if it receives a request to enter low-power mode while it is receiving.
A LIN slave node that is "awake" does not generate a wakeup interrupt if it receives a wakeup pulse.
The default is Disabled.
To add a new processor to the drop down list for the Processors option, click the Add new button on the Board pane. The software opens the Add Processor dialog box.
Note You can use this feature to create duplicates of existing processors with minor changes to the compiler and linker options. Avoid using this feature to create profiles for processors that are not already supported. |
Provide a name to identify your new processor. Use any valid C string. The name you enter in this field appears on the list of processors after you add the new processor.
If you do not provide an entry for each parameter, the coder product returns an error message without creating a processor entry.
When you add a processor, the dialog box uses the settings from the currently selected processor as the basis for the new one. This parameter displays the currently selected processor.
Identifies the processor family of the new processor to the compiler. Successful compilation requires this switch. The string depends on the processor family or class.
For example, to set the compiler switch for a new C5509 processor, enter -ml. The following table shows the compiler switch string for supported processor families.
| Processor Family | Compiler Switch String |
|---|---|
| C62xx | None |
| C64xx | None |
| C67xx | None |
| DM64x and DM64xx | None |
| C55xx | -ml |
| C28xx, F28xx, R28xx, F28xxx | -ml |
You can use this parameter to specify linker command options. The IDE uses these options to modify how it links project files when you build a project. To get information about specific linker options you can enter here, consult the documentation for your IDE.
The Linux tab appears when you set IDE/Tool Chain to Eclipse and set Operating System on the Board tab to Linux.
The Linux tab displays two options:
When you select free-running, the model generates multi-threaded free-running code. Each rate in the model maps to a separate thread in the generated code. Multi-threaded code can potentially run faster than single threaded code.
When you select real-time, the model generates multi-threaded real-time code: Each rate in the Simulink model runs at the rate specified in the model. For example, a 1-second rate runs at exactly 1-second intervals. The timing is provided by using a Linux real-time clock.
The base rate in the model maps to a thread and runs as fast as possible. You can use the value of the base rate priority to set a static priority for the base rate task. By default, this rate is 40.
Enable multicore deployment. Selecting this option enables generated multi-threading code to run concurrently on multicore processors. By default, this option is disabled.
This parameter has been superseded. Configuring the model as described in the following procedures hides the Allow tasks to execute concurrently parameter from view.
To run target applications on multicore processors, follow the procedures in Running Target Applications on Multicore Processors, and Configuring Models for Targets with Multicore Processors.
The VxWorks tab appears when you set IDE/Tool Chain to Wind River Diab/GCC (makefile generation only) and set Operating System on the Board tab to VxWorks.
The Linux tab displays two options:
When you select free-running, the model generates multi-threaded free-running code. Each rate in the model maps to a separate thread in the generated code. Multi-threaded code can potentially run faster than single threaded code.
When you select real-time, the model generates multi-threaded real-time code: Each rate in the Simulink model runs at the rate specified in the model. For example, a 1-second rate runs at exactly 1-second intervals. The timing is provided by using a Linux real-time clock.
The base rate in the model maps to a thread and runs as fast as possible. You can use the value of the base rate priority to set a static priority for the base rate task. By default, this rate is 40.
Enable multicore deployment. Selecting this option enables generated multi-threading code to run concurrently on multicore processors. By default, this option is disabled.
This parameter has been superseded. Configuring the model as described in the following procedures hides the Allow tasks to execute concurrently parameter from view.
To run target applications on multicore processors, follow the procedures in Running Target Applications on Multicore Processors, and Configuring Models for Targets with Multicore Processors.
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
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