HDL Verifier - Documentation

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Contents

Index

• Getting Started

• Introduction

• Product Description

• HDL Cosimulation

HDL Cosimulation with MATLAB or Simulink and the HDL Simulator

Communications for HDL Cosimulation

Hardware Description Language (HDL) Support

HDL Cosimulation Workflows Described in the User Guide

• FPGA Development

FPGA Development with HDL Verifier

FPGA-in-the-Loop Simulation

FPGA Automation with Filter Design HDL Coder

• TLM Component Generation

Generating TLM Components for Use with Virtual Platform Development

Typical Users and Applications

• Installation

Installing the HDL Verifier Software

Installing Related Application Software

• Product Requirements

• What You Need to Know

For Cosimulating with HDL Simulators

For FPGA-in-the-Loop Simulation

For FPGA Automation

For Generating OSCI-Compatible TLM Components

Additional Useful Experience

Product Limitations

• Required Products

Supported EDA Tools

System Requirements

Product Feature and Platform Support

Optional Application Software

• Getting Help

Information Overview

Using "What's This?" Context-Sensitive Help

• Demos and Tutorials

• HDL Code Importing

• Generate HDL Cosimulation Interfaces from Existing HDL Code

Create a MATLAB Function From Existing HDL Code

Create a MATLAB System Object From Existing HDL Code

Create an HDL Cosimulation Block From Existing HDL Code

Perform Cosimulation

• Import HDL Code For FPGA-in-the-Loop Verification

Preparing to Use the FPGA-in-the-Loop (FIL) Wizard

Running the FIL Wizard

Performing FIL Simulation

• User's Guide

• HDL Verification with Cosimulation

• HDL Cosimulation Using MATLAB Test Bench Function

• HDL Cosimulation Using MATLAB Component Function

• HDL Cosimulation Using MATLAB System Object

• Simulating an HDL Component in a Simulink Test Bench Environment

• Replacing an HDL Component with a Simulink Algorithm

• Recording Simulink Signal State Transitions for Post-Processing

• HDL Cosimulation Wizard

• HDL Cosimulation Reference

• System Objects

• FPGA-in-the-Loop and FPGA Automation

• FPGA-in-the-Loop (FIL)

• FPGA Automation with Filter Design HDL Coder

• FPGA Automation Options Reference

• SystemC TLM 2.0 Generation

How TLM Component Generation Works

• TLM Component Architecture

• Generate TLM Component

• Run TLM Component Test Bench

• Export TLM Component to SystemC Environment

• Configuration Parameters for TLM Generator Target

• Release Notes

HDL Verifier roadmap page

	Functions:
	By Category
	Alphabetical List

	Blocks:
	By Category
	Alphabetical List

	System Objects
	Alphabetical List



	Documentation Set

	Getting Started
	Introduces HDL Verifier and gets you started using it

	User's Guide
	Provides tutorials and comprehensive information about HDL Verifier

	Examples in Documentation
	Lists major examples in the HDL Verifier documentation



	Product Demos

	HDL Verifier Demos
	Presents a collection of demos that help you learn the product



	What's New

	Release Notes
	Summarizes new features, bug fixes, upgrade issues, etc.



	Printable (PDF) Documentation on the Web

	PDF Documents
	Provides printable versions of documentation for HDL Verifier

MathWorks Web Site Resources

	Demos
	MATLAB Central
	Product Page
	Platforms & Requirements

	Related Books
	Related Products
	Technical Support

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