Import HDL Code For FPGA-in-the-Loop Verification

On this page…
Preparing to Use the FPGA-in-the-Loop (FIL) Wizard Running the FIL Wizard Performing FIL Simulation

Preparing to Use the FPGA-in-the-Loop (FIL) Wizard

Before beginning:

1. Have your HDL code ready and the original model opened.

2. Set up your project tools by specifying the path to the executables. See Generate FIL Block in the User Guide.

For more detailed information, see FPGA-in-the-Loop (FIL). For a demonstration of FIL, see the FPGA-in-the-Loop demos under HDL Verifier.

 Altera Board with Linux

Back to Top

Running the FIL Wizard

1. At the MATLAB prompt, enter the following:

   >> filWizard

2. Select the FPGA vendor you are using (FPGA design software) to display boards supported for that vendor. Choose either Altera or Xilinx. If you leave the selection at All, all supported boards will be displayed in the pull-down menu.

3. Select the board you are using. Adjust the Board IP address if applicable. Click Next to continue.

   

4. Select your HDL source files. Indicate the top-level module. Click Next to continue.

   

5. Review the DUT I/O ports. Change any settings if desired. Click Next to continue.

   

   There must be at least one input and one output data port.

6. Select the output folder for the programming files. Click Next to continue.

   

7. Click Build.

During the build process, the following actions occur:

• The FIL Wizard generates a FIL block named after the top-level module and places it in a new model.

  

• After new model generation, the FIL Wizard opens a command window.

  • In this window, the FPGA design software performs synthesis, fit, place-and-route, timing analysis, and FPGA programming file generation.

  • When the process is finished, a message in the command window lets you know you can close the window.

For more detailed information about the FIL Wizard, see Generating a FIL Block Using the FIL Wizard. For more information about the FIL process, see FPGA-in-the-Loop (FIL). For a demonstration of FIL, see the FPGA-in-the-Loop demos under HDL Verifier.

Back to Top

Performing FIL Simulation

1. Insert the generated FIL block into the existing model.

2. Open the block mask and load the programming files.

   

    Altera Board with Linux

   If you are using the Altera board and a Linux distribution supported by Altera, you should first read the "USB-Blaster Download Cable User Guide" provided on the Altera web site: http://www.altera.com/literature/ug/ug_usb_blstr.pdf. Specifically, to program the bit file you must be a superuser. The user guide provides instructions for making a one-time modification to a rules file to give you that permission.

3. Make any other adjustments on the block mask, if desired.

   

4. Run the FIL simulation.

For more detailed information, see FPGA-in-the-Loop (FIL). For a demonstration of FIL, see the FPGA-in-the-Loop demos under HDL Verifier.

Back to Top

Generate HDL Cosimulation Interfaces from Existing HDL Code

© 1984-2012- The MathWorks, Inc.    -   Site Help   -   Patents   -   Trademarks   -   Privacy Policy   -   Preventing Piracy   -   RSS