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R2011b Documentation → EDA Simulator Link
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Contents

Index

• Getting Started

Product Description

Product Limitations

HDL Cosimulation with MATLAB or Simulink and the HDL Simulator

Communications for HDL Cosimulation

Hardware Description Language (HDL) Support

HDL Cosimulation Workflows Described in the User Guide

Generating TLM Components for Use with Virtual Platform Development

Typical Users and Applications

FPGA-in-the-Loop Simulation

FPGA Automation

Supported EDA Tools

System Requirements

Product Feature and Platform Support

Optional Application Software

Overview to the Cosimulation Wizard

Creating a Function from Existing HDL Code

Creating a Block from Existing HDL Code

Using the Cosimulation Wizard

Performing Cosimulation

Preparing to Use the FPGA-in-the-Loop (FIL) Wizard

Running the FIL Wizard

Performing FIL Simulation

• User's Guide

• HDL Verification with Cosimulation

• Simulating an HDL Component in a MATLAB Test Bench Environment

• MATLAB Component to Represent HDL Design

• Simulating an HDL Component in a Simulink Test Bench Environment

• Replacing an HDL Component with a Simulink Algorithm

• Component Simulation with Simulink

Understanding How the HDL Simulator and Simulink Software Communicate Using EDA Simulator Link For Component Simulation

HDL Cosimulation Block Features for Component Simulation

Using Simulink to Replace an HDL Component

• Code an HDL Component for Use with Simulink Applications

Overview to Coding HDL Modules for Simulink Component Simulation

Specifying Port Direction Modes in the HDL Module for Component Simulation

Specifying Port Data Types in the HDL Module for Component Simulation

Compiling and Elaborating the HDL Design for Component Simulation

• Create Simulink Model for Component Cosimulation with the HDL Simulator

Creating the Simulink Model for Component Cosimulation

Running and Testing a Component Hardware Model in Simulink

Adding a Value Change Dump (VCD) File to Component Model (Optional)

• Launch HDL Simulator for Component Cosimulation with Simulink

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Component Cosimulation

• Add the HDL Cosimulation Block to the Simulink Component Model

Insert HDL Cosimulation Block

Connect Block Ports

• Define the HDL Cosimulation Block Interface for Component Simulation

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

• Run a Component Cosimulation Session

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Component Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Component Cosimulation and the EDA Simulator Link HDL Cosimulation Block

• Recording Simulink Signal State Transitions for Post-Processing

• HDL Cosimulation Wizard

• HDL Cosimulation Reference

• FPGA-in-the-Loop and FPGA Automation

• SystemC TLM 2.0 Generation

• Release Notes

Replacing an HDL Component with a Simulink Algorithm

Verify HDL Model with Simulink Test Bench (Tutorial)

Verify HDL Model with Simulink Test Bench (Tutorial)

Component Simulation with Simulink

Component Simulation with Simulink

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