Simulating an HDL Component in a Simulink Test Bench Environment (EDA Simulator Link™ User's Guide)

• Getting Started

Product Description

Product Limitations

HDL Cosimulation with MATLAB or Simulink and the HDL Simulator

Communications for HDL Cosimulation

Hardware Description Language (HDL) Support

HDL Cosimulation Workflows Described in the User Guide

Generating TLM Components for Use with Virtual Platform Development

Typical Users and Applications

FPGA-in-the-Loop Simulation

FPGA Automation

Supported EDA Tools

System Requirements

Product Feature and Platform Support

Optional Application Software

Demos

Tutorials

Overview to the Cosimulation Wizard

Creating a Function from Existing HDL Code

Creating a Block from Existing HDL Code

Using the Cosimulation Wizard

Performing Cosimulation

Preparing to Use the FPGA-in-the-Loop (FIL) Wizard

Running the FIL Wizard

Performing FIL Simulation

• User's Guide

• HDL Verification with Cosimulation

• Simulating an HDL Component in a MATLAB Test Bench Environment

• MATLAB Component to Represent HDL Design

• Simulating an HDL Component in a Simulink Test Bench Environment

• Using Simulink as a Test Bench

Understanding How the HDL Simulator and Simulink Software Communicate Using EDA Simulator Link For Test Bench Simulation

HDL Cosimulation Block Features for Test Bench Simulation

Simulating an HDL Component in a Simulink Test Bench

• Create a Simulink Model for Test Bench Cosimulation with the HDL Simulator

Creating Your Simulink Model

Running Test Bench Hardware Model in Simulink

Adding a Value Change Dump (VCD) File (Optional)

• Code an HDL Component for Use with Simulink Test Bench Applications

Overview to Coding HDL Components for Simulink Test Bench Sessions

Specifying Port Direction Modes in the HDL Component for Test Bench Use

Specifying Port Data Types in the HDL Component for Test Bench Use

Compiling and Elaborating the HDL Design for Test Bench Use

• Launch HDL Simulator for Test Bench Cosimulation with Simulink

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Test Bench Cosimulation

• Add the HDL Cosimulation Block to the Simulink Test Bench Model

Insert HDL Cosimulation Block

Connect Block Ports

• Define the HDL Cosimulation Block Interface for Test Bench Cosimulation

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

• Run a Test Bench Cosimulation Session

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Test Bench Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Test Bench Cosimulation and the EDA Simulator Link HDL Cosimulation Block

• Verify HDL Model with Simulink Test Bench (Tutorial)

Tutorial Overview

Developing the VHDL Code

Compiling the VHDL File

Creating the Simulink Model

Setting Up ModelSim for Use with Simulink

Loading Instances of the VHDL Entity for Cosimulation with Simulink

Running the Simulation

Shutting Down the Simulation

• Replacing an HDL Component with a Simulink Algorithm

• Recording Simulink Signal State Transitions for Post-Processing

• HDL Cosimulation Wizard

• HDL Cosimulation Reference

• FPGA-in-the-Loop and FPGA Automation

• SystemC TLM 2.0 Generation

• Blocks

• Functions

Examples

• Release Notes

Search MATLAB Documentation
R2011b Documentation → EDA Simulator Link
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Simulating an HDL Component in a Simulink Test Bench Environment

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