Start Connection to HDL Simulator for Component Function Session :: HDL Cosimulation Using MATLAB Component Function (HDL Verifier™ User's Guide)

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Contents

Index

• Getting Started

• User's Guide

• HDL Verification with Cosimulation

• HDL Cosimulation Using MATLAB Test Bench Function

• HDL Cosimulation Using MATLAB Component Function

Using a MATLAB Function as a Component

Create a MATLAB Component Function for Use with the HDL Simulator

• Code HDL Modules for Visualization Using MATLAB

• Create an HDL Verifier MATLAB Component Function

• Place Component Function on MATLAB Search Path

• Start Connection to HDL Simulator for Component Function Session

Start MATLAB Server for Component Function Session

Example of Starting MATLAB Server for Component Function Session

• Launch HDL Simulator for Use with MATLAB Component Session

Launching the HDL Simulator for Component Session

Loading an HDL Design for Visualization

• Invoke matlabcp to Bind MATLAB Component Function Calls

Invoking the MATLAB Component Function Command matlabcp

Binding the HDL Module Component to the MATLAB Component Function

• Schedule Options for a Component Session

About Scheduling Options for Component Sessions

Scheduling Component Session Using matlabcp Arguments

Scheduling Component Functions Using the tnext Parameter

• Run MATLAB Component Function Simulation

Process for Running MATLAB Component Function Cosimulation

Checking the MATLAB Server's Link Status for Component Cosimulation

Running a Component Function Cosimulation

Applying Stimuli to Component Function with the HDL Simulator force Command

Restarting a Component Simulation

Stop Component Simulation

• HDL Cosimulation Using MATLAB System Object

Verifying Viterbi Decoder Using MATLAB System Object and Mentor Graphics ModelSim

• Simulating an HDL Component in a Simulink Test Bench Environment

Understanding How the HDL Simulator and Simulink Software Communicate Using HDL Verifier For Test Bench Simulation

HDL Cosimulation Block Features for Test Bench Simulation

Creating Your Simulink Model

Running Test Bench Hardware Model in Simulink

Adding a Value Change Dump (VCD) File (Optional)

Overview to Coding HDL Components for Simulink Test Bench Sessions

Specifying Port Direction Modes in the HDL Component for Test Bench Use

Specifying Port Data Types in the HDL Component for Test Bench Use

Compiling and Elaborating the HDL Design for Test Bench Use

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Test Bench Cosimulation

Insert HDL Cosimulation Block

Connect Block Ports

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Test Bench Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Test Bench Cosimulation and the HDL Verifier HDL Cosimulation Block

Tutorial Overview

Developing the VHDL Code

Compiling the VHDL File

Creating the Simulink Model

Setting Up ModelSim for Use with Simulink

Loading Instances of the VHDL Entity for Cosimulation with Simulink

Running the Simulation

Shutting Down the Simulation

• Replacing an HDL Component with a Simulink Algorithm

Understanding How the HDL Simulator and Simulink Software Communicate Using HDL Verifier For Component Simulation

HDL Cosimulation Block Features for Component Simulation

Overview to Coding HDL Modules for Simulink Component Simulation

Specifying Port Direction Modes in the HDL Module for Component Simulation

Specifying Port Data Types in the HDL Module for Component Simulation

Compiling and Elaborating the HDL Design for Component Simulation

Creating the Simulink Model for Component Cosimulation

Running and Testing a Component Hardware Model in Simulink

Adding a Value Change Dump (VCD) File to Component Model (Optional)

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Component Cosimulation

Insert HDL Cosimulation Block

Connect Block Ports

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Component Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Component Cosimulation and the HDL Verifier HDL Cosimulation Block

• Recording Simulink Signal State Transitions for Post-Processing

Introduction to the To VCD File Block

Using the To VCD File Block

Tutorial: Overview

Tutorial: Instructions

• HDL Cosimulation Wizard

Workflow for Using the Cosimulation Wizard to Create Test Bench or Component Function

Workflow for Using the Cosimulation Wizard to Create a MATLAB System Object

Workflow for Using the Cosimulation Wizard to Create a Simulink Block

Common Workflows

MATLAB Workflow

MATLAB System Object Workflow

Simulink Workflow

Cosimulation Wizard for MATLAB System Object

Verify Raised Cosine Filter Design With Generated MATLAB Component

Verify Raised Cosine Filter Design With Generated Simulink Test Bench

• HDL Cosimulation Reference

Machine Configuration Requirements

HDL Simulator Startup

HDL Verifier Libraries

Setup Diagnostics and Customization

Adding Questa ADMS Support

Cross-Network Cosimulation

Writing Functions Using the HDL Instance Object

Writing Functions Using Port Information

Applying Direct Feedthrough to Eliminate Block Simulation Latency

Obtaining Baseline Performance Numbers

Analyzing Simulation Performance

Cosimulating Frame-Based Signals with Simulink

Overview to Avoiding Race Conditions

Potential Race Conditions in Simulink Cosimulation Sessions

Potential Race Conditions in MATLAB Cosimulation Sessions

Further Reading

Converting HDL Data to Send to MATLAB

Array Indexing Differences Between MATLAB and HDL

Converting Data for Manipulation

Converting Data for Return to the HDL Simulator

Overview to the Representation of Simulation Time

Defining the Simulink and HDL Simulator Timing Relationship

Setting the Timing Mode with HDL Verifier

Relative Timing Mode

Absolute Timing Mode

Timing Mode Usage Considerations

Setting HDL Cosimulation Block Port Sample Times

Options for Driving Clocks, Resets, and Enables

Adding Signals Using Simulink Blocks

Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block

Driving Signals by Adding Force commands

• System Objects

Create a System Object

Define a New System Object

Change a System Object Property

Run a System Object

Display Available System Objects

Create a New System Object

Retrieve System Object Property Values

Set System Object Property Values

What are System Object Methods?

The Step Method

Advantages of Using Methods

Understand System Object Modes

Change Properties While Running System Objects

Change System Object Input Complexity or Dimensions

• FPGA-in-the-Loop and FPGA Automation

FIL Simulation User Workflow

Communication Channel

Downstream Workflow Automation

• SystemC TLM 2.0 Generation

Automatically Generated Memory Map with Single Address

Automatically Generated Memory Map with Individual Addresses

Write-Only Bits

Read-and-Write Bits

Register Definition

Temporal Decoupling Overview

Temporal Decoupling and No Buffering

Temporal Decoupling and Buffering

Basic Workflow Steps

How to Set TLM Component Generation Options

TLM Component Test Bench Overview

TLM Component Compilation

Automatic Verification of the Generated Component

Report Generation

Working with Configurations

Considerations When Creating a TLM Component Test Bench

Verbose Messaging

Run-Time Timing Mode

Input and Output Buffer Triggering Modes

Verify TLM Component

About the TLM Component Compiler Options

SystemC Include Path

SystemC Library Path

SystemC Library Name

TLM Include Path

How to Identify Generated Files

Create Static Library with the TLM Component

Create Standalone Executable with the TLM Component and Test Bench

TLM Component Generation Overview

Memory Map Type

Auto-Generated Memory Map Type

Include a command and status register in the memory map

Include a test and set register in the memory map

Algorithm Step Function Execution

Algorithm step function timing (ns)

Enable temporal decoupling for loosely-timed simulation

Maximum quantum for loosely-timed components (ns)

Enable payload buffering

Payload input buffer depth

Payload output buffer depth

Create an interrupt request port on the generated TLM component

Single write transfer or the first write transfer in a burst transaction (ns)

Subsequent write transfers in a burst transaction (ns)

Single read transaction or the first read transfer in a burst transaction (ns)

Subsequent read transfers in a burst transaction (in ns)

User-tag for TLM component names

TLM Component Testbench Pane Overview

Generate testbench

Generate verbose messages during testbench execution

Run-time timing mode

Input buffer triggering mode

Output buffer triggering mode

TLM Component Compilation Overview

SystemC include path

SystemC library path

SystemC library name

TLM include path

• Release Notes

Start Connection to HDL Simulator for Component Function Session

On this page…

Start MATLAB Server for Component Function Session

Example of Starting MATLAB Server for Component Function Session

Start MATLAB Server for Component Function Session

Start the MATLAB server as follows:

Start MATLAB.
In the MATLAB Command Window, call the hdldaemon function with property name/property value pairs that specify whether the HDL Verifier software is to perform the following tasks:
- Use shared memory or TCP/IP socket communication
- Return time values in seconds or as 64-bit integers

See hdldaemon reference documentation for when and how to specify property name/property value pairs and for more examples of using hdldaemon.

The communication mode that you specify (shared memory or TCP/IP sockets) must match what you specify for the communication mode when you initialize the HDL simulator for use with a MATLAB cosimulation session using the matlabtb or matlabcp function. In addition, if you specify TCP/IP socket mode, the socket port that you specify with hdldaemon and matlabtb or matlabcp must match. For more information on modes of communication, see Choosing TCP/IP Socket Ports.

The MATLAB server can service multiple simultaneous HDL simulator modules and clients. However, your code must track the I/O associated with each entity or client.

Note You cannot begin an HDL Verifier transaction between MATLAB and the HDL simulator from MATLAB. The MATLAB server simply responds to function call requests that it receives from the HDL simulator.

Example of Starting MATLAB Server for Component Function Session

The following command specifies using socket communication on port 4449 and a 64-bit time resolution format for the MATLAB function's output ports.

hdldaemon('socket', 4449, 'time', 'int64')

Place Component Function on MATLAB Search Path

Place Component Function on MATLAB Search Path

Launch HDL Simulator for Use with MATLAB Component Session

Launch HDL Simulator for Use with MATLAB Component Session

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